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copyright ? cirrus logic, inc. 2001 (all rights reserved) CS8900A product data sheet
? isa ethernet controller features single-chip ieee 802.3 ethernet controller with direct isa-bus interface maximum current consumption = 55 ma (5v supply ) 3 v operation industrial temperature range comprehensive suite of software drivers available efficient packetpage? architecture operates in i/o and memory space, and as dma slave full duplex operation on-chip ram buffers transmit and receive frames 10base-t port with analog filters, provides: ? automatic polarity detection and correction aui port for 10base2, 10base5 and 10base-f programmable transmit features: ? automatic re-transmission on collision ? automatic padding and crc generation programmable receive features: ? stream transfer? for reduced cpu overhead ? auto-switch between dma and on-chip memory ? early interrupts for frame pre-processing ? automatic rejection of erroneous packets eeprom support for jumperless configuration boot prom support for diskless systems boundary scan and loopback test led drivers for link status and lan activity standby and suspend sleep modes description the CS8900A is a low-cost ethernet lan controller op- timized for industry standard architecture (isa) personal computers. its highly-integrated design elimi- nates the need for costly external components required by other ethernet controllers. the CS8900A includes on-chip ram, 10base-t transmit and receive filters, and a direct isa-bus interface with 24 ma drivers. in addition to high integration, the CS8900A offers a broad range of performance features and configuration- options. its unique packetpage architecture automatically adapts to changing network traffic pat- terns and available system resources. the result is increased system efficiency. the CS8900A is available in a 100-pin tqfp package ideally suited for small form-factor, cost-sensitive ether- net applications. with the CS8900A, system engineers can design a complete ethernet circuit that occupies less than 1.5 square inches (10 sq. cm) of board space. ordering information CS8900A-cq 0 to 70 c 5v tqfp-100 CS8900A-iq -40 to 85 c 5v tqfp-100 CS8900A-cq3 0 to 70 c 3.3v tqfp-100 CS8900A-iq3 -40 to 85 c 3.3v tqfp-100 crd8900a-1 evaluation kit eeprom rj-45 10base-t attachment unit interface (aui) 20 mhz xtal ram isa bus logic memory manager 802.3 mac engine eeprom control encoder/ decoder & pll 10base-t rx filters & receiver 10base-t tx filters & transmitter aui transmitter aui collision aui receiver clock power manager boundary scan test logic led control CS8900A isa ethernet controller i s a ds271pp4 apr ? 01 cirrus logic product datasheet
2 ds271pp4 CS8900A crystal lan? isa ethernet controller cirrus logic product datasheet table of contents 1.0 introduction .............................................................................................................. ........7 1.1 general description ....................................................................................................... .....7 1.1.1 tdirect isa-bus interface ......................................................................................7 1.1.2 tintegrated memory ..............................................................................................7 1.1.3 t802.3 ethernet mac engine ................................................................................7 1.1.4 teeprom interface ..............................................................................................7 1.1.5 tcomplete analog front end ................................................................................7 1.2 system applications ....................................................................................................... ....7 1.2.1 tmotherboard lans ..............................................................................................7 1.2.2 tethernet adapter cards .......................................................................................8 1.3 key features and benefits ................................................................................................. 9 1.3.1 tvery low cost .....................................................................................................9 1.3.2 thigh performance ................................................................................................9 1.3.3 tlow power and low noise ..................................................................................9 1.3.4 tcomplete support ...............................................................................................9 2.0 pin description ........................................................................................................ .....11 3.0 functional description ...............................................................................................16 3.1 overview .................................................................................................................. ........16 3.1.1 tconfiguration .....................................................................................................16 3.1.2 tpacket transmission .........................................................................................16 3.1.3 tpacket reception ..............................................................................................16 3.2 isa bus interface ......................................................................................................... ....17 3.2.1 tmemory mode operation ...................................................................................17 3.2.2 ti/o mode operation ...........................................................................................17 3.2.3 tinterrupt request signals ..................................................................................17 3.2.4 tdma signals ......................................................................................................17 3.3 reset and initialization .................................................................................................. ...18 3.3.1 treset .................................................................................................................1 8 3.3.1.1 external reset, or isa reset ...............................................................18 3.3.1.2 power-up reset ..................................................................................18 3.3.1.3 power-down reset ..............................................................................18 3.3.1.4 eeprom reset ...................................................................................18 3.3.1.5 software initiated reset .......................................................................18 3.3.1.6 hardware (hw) standby or suspend ..................................................18 3.3.1.7 sof tware (sw) suspend .....................................................................18 3.3.2 tallowing time for reset operation ....................................................................18 3.3.3 tbus reset considerations .................................................................................18 3.3.4 tinitialization ........................................................................................................1 9 3.4 configurations with eeprom ..........................................................................................20 3.4.1 teeprom interface ............................................................................................20 3.4.2 teeprom memory organization ........................................................................20 3.4.3 treset configuration block .................................................................................20 3.4.3.1 reset configuration block structure ....................................................20 3.4.3.2 reset configuration block header ......................................................20 3.4.3.3 determining the eeprom type ..........................................................20 3.4.3.4 checking eeprom for presence of reset configuration block ..........20 3.4.3.5 determining number of bytes in the reset configuration block .........21 3.4.4 tgroups of configuration data ............................................................................21 3.4.4.1 group header ......................................................................................22 3.4.5 treset configuration block checksum ...............................................................22 3.4.6 teeprom example ............................................................................................22 3.4.7 teeprom read-out ...........................................................................................22
ds271pp4 3 CS8900A crystal lan? isa ethernet controller cirrus logic product datasheet 3.4.7.1 determining eeprom size .................................................................22 3.4.7.2 loading configuration data .................................................................23 3.4.8 teeprom read-out completion ........................................................................23 3.5 programming the eeprom .............................................................................................23 3.5.1 teeprom commands .......................................................................................23 3.5.2 teeprom command execution ........................................................................23 3.5.3 tenabling access to the eeprom .....................................................................24 3.5.4 twriting and erasing the eeprom ....................................................................24 3.6 boot prom operation .....................................................................................................24 3.6.1 taccessing the boot prom ................................................................................24 3.6.2 tconfiguring the CS8900A for boot prom operation .......................................24 3.7 low-power modes .......................................................................................................... 25 3.7.1 thardware standby ............................................................................................25 3.7.2 thardware suspend ...........................................................................................25 3.7.3 tsoftware suspend .............................................................................................26 3.8 led outputs ............................................................................................................... ......27 3.8.0.1 lanled ..............................................................................................27 3.8.0.2 linkled or hc0 .................................................................................27 3.8.0.3 bstatus or hc1 ...............................................................................27 3.8.1 tled connection ................................................................................................27 3.9 media access control ...................................................................................................... 27 3.9.1 toverview ...........................................................................................................27 3.9.2 tframe encapsulation and decapsulation .........................................................28 3.9.2.1 transmission .......................................................................................28 3.9.2.2 reception ............................................................................................28 3.9.2.3 enforcing minimum frame size ..........................................................28 3.9.3 ttransmit error detection and handling .............................................................29 3.9.3.1 loss of carrier .....................................................................................29 3.9.3.2 sqe error ............................................................................................29 3.9.3.3 out-of-window (late) collision ............................................................29 3.9.3.4 jabber error ........................................................................................29 3.9.3.5 transmit collision ................................................................................29 3.9.3.6 transmit underrun ..............................................................................29 3.9.4 treceive error detection and handling ..............................................................30 3.9.4.1 crc error ............................................................................................30 3.9.4.2 runt frame .........................................................................................30 3.9.4.3 extra data ...........................................................................................30 3.9.4.4 dribble bits and alignment error .........................................................30 3.9.5 tmedia access management ..............................................................................30 3.9.5.1 collision avoidance .............................................................................30 3.9.5.2 two-part deferral ................................................................................30 3.9.5.3 simple deferral ....................................................................................31 3.9.5.4 collision resolution .............................................................................31 3.9.5.5 normal collisions ................................................................................31 3.9.5.6 late collisions .....................................................................................32 3.9.5.7 backoff ................................................................................................32 3.9.5.8 standard backoff .................................................................................32 3.9.5.9 modified backoff ..................................................................................32 3.9.5.10 sqe test ...........................................................................................32 3.10 encoder/decoder (endec) ...........................................................................................33 3.10.1 tencoder ...........................................................................................................33 3.10.2 tcarrier detection .............................................................................................33 3.10.3 tclock and data recovery ...............................................................................33
4 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 3.10.4 tinterface selection ...........................................................................................34 3.10.4.1 10base-t only .................................................................................34 3.10.4.2 aui only ............................................................................................34 3.10.4.3 auto-select ........................................................................................34 3.11 10base-t transceiver ...................................................................................................34 3.11.1 t10base-t filters .............................................................................................34 3.11.2 ttransmitter ......................................................................................................35 3.11.3 treceiver ..........................................................................................................35 3.11.3.1 squelch circuit ...................................................................................35 3.11.3.2 extended range ................................................................................35 3.11.4 tlink pulse detection ........................................................................................35 3.11.5 treceive polarity detection and correction ......................................................36 3.11.6 tcollision detection ...........................................................................................36 3.12 attachment unit interface (aui) .....................................................................................36 3.12.1 taui transmitter ...............................................................................................36 3.12.2 taui receiver ...................................................................................................37 3.12.3 tcollision detection ...........................................................................................37 3.13 external clock oscillator ................................................................................................ 37 4.0 packetpage architecture ..........................................................................................38 4.1 packetpage overview ......................................................................................................3 8 4.1.1 tintegrated memory ............................................................................................38 4.1.2 tbus interface registers .....................................................................................38 4.1.3 tstatus and control registers .............................................................................38 4.1.4 tinitiate transmit registers .................................................................................38 4.1.5 taddress filter registers ....................................................................................38 4.1.6 treceive and transmit frame locations ............................................................38 4.2 packetpage memory map ................................................................................................39 4.3 bus interface registers ................................................................................................... .41 4.4 status and control registers ...........................................................................................46 4.4.1 tconfiguration and control registers .................................................................46 4.4.2 tstatus and event registers ...............................................................................46 4.4.3 tstatus and control bit definitions ......................................................................46 4.4.3.1 act-once bits .......................................................................................47 4.4.3.2 temporal bits .......................................................................................47 4.4.3.3 interrupt enable bits and events .........................................................47 4.4.3.4 accept bits ...........................................................................................47 4.4.4 tstatus and control register summary ..............................................................48 4.5 initiate transmit registers ............................................................................................... .70 4.6 address filter registers .................................................................................................. .71 4.7 receive and transmit frame locations ...........................................................................72 4.7.1 treceive packetpage locations .........................................................................72 4.7.2 ttransmit locations ............................................................................................72 4.8 eight and sixteen bit transfers ........................................................................................72 4.8.1 ttransferring odd-byte-aligned data .................................................................73 4.8.2 trandom access to CS8900A memory ..............................................................73 4.9 memory mode operation ..................................................................................................73 4.9.1 taccesses in memory mode ...............................................................................73 4.9.2 tconfiguring the CS8900A for memory mode .....................................................73 4.9.3 tbasic memory mode transmit ...........................................................................74 4.9.4 tbasic memory mode receive ............................................................................74 4.9.5 tpolling the CS8900A in memory mode ..............................................................75 4.10 i/o space operation ..................................................................................................... .75 4.10.1 treceive/transmit data ports 0 and 1 ..............................................................75
ds271pp4 5 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.10.2 ttxcmd port ....................................................................................................75 4.10.3 ttxlength port ..................................................................................................75 4.10.4 tinterrupt status queue port ............................................................................75 4.10.5 tpacketpage pointer port .................................................................................75 4.10.6 tpacketpage data ports 0 and 1 ......................................................................76 4.10.7 ti/o mode operation .........................................................................................76 4.10.8 tbasic i/o mode transmit .................................................................................76 4.10.9 tbasic i/o mode receive ..................................................................................76 4.10.10 taccessing internal registers .........................................................................77 4.10.11 tpolling the CS8900A in i/o mode .................................................................77 5.0 operation ................................................................................................................. .........78 5.1 managing interrupts and servicing the interrupt status queue .......................................78 5.2 basic receive operation ..................................................................................................7 8 5.2.0.1 overview .............................................................................................78 5.2.1 tterminology: packet, frame, and transfer .......................................................80 5.2.1.1 packet .................................................................................................80 5.2.1.2 frame ..................................................................................................80 5.2.1.3 transfer ...............................................................................................80 5.2.2 treceive configuration .......................................................................................80 5.2.2.1 configuring the physical interface .......................................................80 5.2.2.2 choosing which frame types to accept .............................................80 5.2.2.3 selecting which events cause interrupts ............................................81 5.2.2.4 choosing how to transfer frames ......................................................81 5.2.3 treceive frame pre-processing ........................................................................81 5.2.3.1 destination address filtering ..............................................................82 5.2.3.2 early interrupt generation ...................................................................83 5.2.3.3 acceptance filtering ............................................................................83 5.2.3.4 normal interrupt generation ................................................................83 5.2.4 theld vs. dmaed receive frames .....................................................................83 5.2.5 tbuffering held receive frames ........................................................................83 5.2.6 ttransferring held receive frames ...................................................................85 5.2.7 treceive frame visibility ....................................................................................85 5.2.8 texample of memory mode receive operation .................................................85 5.2.9 treceive frame byte counter ............................................................................86 5.3 receive frame address filtering .....................................................................................86 5.3.0.1 individual address frames ..................................................................87 5.3.0.2 multicast frames .................................................................................87 5.3.0.3 broadcast frames ...............................................................................87 5.3.1 tconfiguring the destination address filter ........................................................87 5.3.2 thash filter .........................................................................................................88 5.3.2.1 hash filter operation ..........................................................................88 5.3.3 tbroadcast frame hashing exception ................................................................88 5.4 receive dma ............................................................................................................... ....89 5.4.1 toverview ...........................................................................................................89 5.4.2 tconfiguring the CS8900A for dma operation ..................................................89 5.4.3 tdma receive buffer size ..................................................................................89 5.4.4 treceive-dma-only operation ...........................................................................90 5.4.5 tcommitting buffer space to a dmaed frame ...................................................91 5.4.6 tdma buffer organization ..................................................................................91 5.4.7 trxdmaframe bit ..............................................................................................91 5.4.8 treceive dma example without wrap-around ..................................................91 5.4.9 treceive dma operation for rxdma-only mode ..............................................91 5.5 auto-switch dma ........................................................................................................... ..92
6 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 5.5.1 toverview ...........................................................................................................92 5.5.2 tconfiguring the CS8900A for auto-switch dma ...............................................93 5.5.3 tauto-switch dma operation ..............................................................................93 5.5.4 tdma channel speed vs. missed frames ..........................................................94 5.5.5 texit from dma ..................................................................................................94 5.5.6 tauto-switch dma example ...............................................................................95 5.6 streamtransfer ............................................................................................................ ....95 5.6.1 toverview ...........................................................................................................95 5.6.2 tconfiguring the CS8900A for streamtransfer ...................................................95 5.6.3 tstreamtransfer operation .................................................................................95 5.6.4 tkeeping streamtransfer mode active ...............................................................95 5.6.5 texample of streamtransfer ...............................................................................97 5.6.6 treceive dma summary ....................................................................................97 5.7 transmit operation ........................................................................................................ ...98 5.7.1 toverview ...........................................................................................................98 5.7.2 ttransmit configuration ......................................................................................98 5.7.2.1 configuring the physical interface .......................................................98 5.7.2.2 selecting which events cause interrupts ............................................98 5.7.3 tchanging the configuration ...............................................................................98 5.7.4 tenabling crc generation and padding ............................................................99 5.7.5 tindividual packet transmission .........................................................................99 5.7.6 ttransmit in poll mode ......................................................................................100 5.7.7 ttransmit in interrupt mode ..............................................................................100 5.7.8 tcompleting transmission ................................................................................101 5.7.9 trdy4txnow vs. rdy4tx ................................................................................101 5.7.10 tcommitting buffer space to a transmit frame .............................................101 5.7.11 ttransmit frame length .................................................................................104 5.8 full duplex considerations .............................................................................................104 5.9 auto-negotiation considerations ....................................................................................104 6.0 test modes ................................................................................................................ ......105 6.0.1 tloopback & collision diagnostic tests ...........................................................105 6.0.2 tinternal tests ...................................................................................................105 6.0.3 texternal tests .................................................................................................105 6.0.4 tloopback tests ...............................................................................................105 6.0.5 t10base-t loopback and collision tests ........................................................105 6.0.6 taui loopback and collision tests ...................................................................105 6.1 boundary scan ............................................................................................................. ..106 6.1.1 toutput cycle ....................................................................................................106 6.1.2 tinput cycle ......................................................................................................106 6.1.3 tcontinuity cycle ...............................................................................................107 7.0 t characteristics/specifications - commercial .............................................110 8.0 t characteristics/specifications - industrial ................................................121 9.0 physical dimensions ....................................................................................................132 10.0 glossary of terms ....................................................................................................133 10.1 acronyms ................................................................................................................. ....133 10.2 definitions .............................................................................................................. .......134 10.3 acronyms specific to the CS8900A .............................................................................135 10.4 terms specific to the CS8900A ...................................................................................135 10.5 suffixes specific to the CS8900A. ................................................................................136 11.0 revision history ......................................................................................................... .137
ds271pp4 7 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 1.0 introduction 1.1 general description the CS8900A is a true single-chip, full-duplex, ethernet solution, incorporating all of the analog and digital circuitry needed for a complete ethernet circuit. major functional blocks include: a direct isa-bus interface; an 802.3 mac engine; integrat- ed buffer memory; a serial eeprom interface; and a complete analog front end with both 10base-t and aui. 1.1.1 direct isa-bus interface included in the CS8900A is a direct isa-bus inter- face with full 24 ma drive capability. its configu- ration options include a choice of four interrupts and three dma channels (one of each selected dur- ing initialization). in memory mode, it supports standard or ready bus cycles without introducing additional wait states. 1.1.2 integrated memory the CS8900A incorporates a 4-kbyte page of on- chip memory, eliminating the cost and board area associated with external memory chips. unlike most other ethernet controllers, the CS8900A buff- ers entire transmit and receive frames on chip, eliminating the need for complex, inefficient mem- ory management schemes. in addition, the CS8900A operates in either memory space, i/o space, or with external dma controllers, providing maximum design flexibility. 1.1.3 802.3 ethernet mac engine the CS8900A?s ethernet media access control (mac) engine is fully compliant with the ieee 802.3 ethernet standard (iso/iec 8802-3, 1993), and supports full-duplex operation. it handles all aspects of ethernet frame transmission and recep- tion, including: collision detection, preamble gen- eration and detection, and crc generation and test. programmable mac features include automatic re- transmission on collision, and automatic padding of transmitted frames. 1.1.4 eeprom interface the CS8900A provides a simple and efficient seri- al eeprom interface that allows configuration in- formation to be stored in an optional eeprom, and then loaded automatically at power-up. this eliminates the need for costly and cumbersome switches and jumpers. 1.1.5 complete analog front end the CS8900A?s analog front end incorporates a manchester encoder/decoder, clock recovery cir- cuit, 10base-t transceiver, and complete attach- ment unit interface (aui). it provides manual and automatic selection of either 10base-t or aui, and offers three on-chip led drivers for link sta- tus, bus status, and ethernet line activity. the 10base-t transceiver includes drivers, re- ceivers, and analog filters, allowing direct connec- tion to low-cost isolation transformers. it supports 100, 120, and 150 ? shielded and unshielded ca- bles, extended cable lengths, and automatic receive polarity reversal detection and correction. the aui port provides a direct interface to 10base-2, 10base-5 and 10base-fl networks, and is capable of driving a full 50-meter aui cable. 1.2 system applications the CS8900A is designed to work well in either motherboard or adapter applications. 1.2.1 motherboard lans the CS8900A requires the minimum number of external components needed for a full ethernet node. its small-footprint package and high level of integration allow system engineers to design a complete ethernet circuit that occupies as little as 1.5 square inches of pcb area (figure 1). in addi- tion, the CS8900A?s power-saving features and cmos design make it a perfect fit for power-sensi-
8 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet tive portable and desktop pcs. motherboard design options include: an eeprom can be used to store node-specif- ic information, such as the ethernet individual address and node configuration. the 20 mhz crystal oscillator may be replaced by a 20 mhz clock signal. 1.2.2 ethernet adapter cards the CS8900A ? s highly efficient packetpage archi- tecture, with streamtransfer ? and auto-switch dma options, make it an excellent choice for high- performance, low-cost isa adapter cards (figure 2). the CS8900A ? s wide range of configu- ration options and performance features allow en- gineers to design ethernet solutions that meet their particular system requirements. adapter card de- sign options include: a boot prom can be added to support diskless applications. the 10base-t transmitter and receiver im- pedance can be adjusted to support 100, 120, or 150 ohm twisted pair cables. an external latchable-address-bus decode cir- cuit can be added to operate the CS8900A in upper-memory space. on-chip led ports can be used for either op- tional leds, or as programmable outputs. rj-45 10base-t CS8900A i s a eeprom 20 mhz xtal (2.0 sq. in.) figure 1. complete ethernet motherboard solution CS8900A eeprom boot prom ? 245 20 mhz xtal rj-45 led attachment unit interface (aui) figure 2. full-featured isa adapter solution
ds271pp4 9 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 1.3 key features and benefits 1.3.1 very low cost the CS8900A is designed to provide the lowest- cost ethernet solution available for embedded ap- plications, portable motherboards, non-isa bus systems and adapter cards. cost-saving features in- clude: integrated ram eliminates the need for expen- sive external memory chips. on-chip 10base-t filters allow designers to use simple isolation transformers instead of more costly filter/transformer packages. the serial eeprom port, used for configura- tion and initialization, eliminates the need for expensive switches and jumpers. the CS8900A is designed to be used on a 2- layer circuit board instead of a more expensive multilayer board. the 8900a-based solution offers the smallest footprint available, saving valuable printed cir- cuit board area. a set of certified software drivers is available at no charge, eliminating the need for costly soft- ware development. 1.3.2 high performance the CS8900A is a full 16-bit ethernet controller designed to provide optimal system performance by minimizing time on the isa bus and cpu over- head per frame. it offers equal or superior perfor- mance for less money when compared to other ethernet controllers. the CS8900A ? s packetpage architecture allows software to select whichever access method is best suited to each particular cpu/isa-bus configuration. when compared to older i/o-space designs, packetpage is faster, sim- pler and more efficient. to boost performance further, the CS8900A in- cludes several key features that increase throughput and lower cpu overhead, including: streamtransfer cuts up to 87% of interrupts to the host cpu during large block transfers. auto-switch dma allows the CS8900A to maximize throughput while minimizing missed frames. early interrupts allow the host to preprocess in- coming frames. on-chip buffering of full frames cuts the amount of host bandwidth needed to manage ethernet traffic. 1.3.3 low power and low noise for low power needs, the CS8900A offers three power-down options: hardware standby, hard- ware suspend, and software suspend. in standby mode, the chip is powered down with the exception of the 10base-t receiver, which is enabled to lis- ten for link activity. in either hardware or software suspend mode, the receiver is disabled and power consumption drops to the micro-ampere range. in addition, the CS8900A has been designed for very low noise emission, thus shortening the time required for emi testing and qualification. 1.3.4 complete support the CS8900A comes with a suite of software driv- ers for immediate use with most industry standard network operating systems. in addition, complete evaluation kits and manufacturing packages are available, significantly reducing the cost and time required to produce new ethernet products.
10 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet eecs eedataout eesk sa[0:19] memw memr iow ior refresh sbhe sd[0:15] intrq0 intrq1 rxd- rxd+ txd- txd+ do- do+ ci- ci+ di- di+ lanled linkled csout eedatain aen reset intrq2 intrq3 dmarq0 dmack0 dmarq1 dmack1 dmarq2 dmack2 memcs16 iochrdy 1: 68 pf 1 3 6 8 24.3 ?, 1% 24.3 ?, 1% 92 91 88 87 100 ?, 1% rj45 16 14 11 9 6 3 2 1 1:1 1 4 5 8 84 82 81 79 16 13 12 9 10 10 9 2 5 83 80 2 7 15 3 12 1:1 1:1 0.1 f 680 ? 680 ? ce oe oe dir 20 22 19 1 74ls245 xtal1 xtal2 sleep test res cs do di clk 1 3 2 4 3 5 4 6 93c46 28 62 61 29 7 irq10 irq11 irq12 irq5 drq5 dack5 drq6 dack6 drq7 dack7 16 20 sa[0:19] la[20:23] bale 4 97 98 93 4.99 k ? , 1% 12 v 4, 6 20 mhz 0.1 f 39.2 ? , 1% 5 v 4.7 k ? CS8900A chipsel iocs16 49 63 75 36 34 64 33 32 30 35 31 15 13 14 16 11 12 99 100 17 39.2 ? , 1% 39.2 ? , 1% 39.2 ? , 1% eeprom address decoder pal 27c256 2 elcs isa bus 10 base t isolation transformer 1:1 15 pin d aui isolation transformer bstatus/hci boot-prom pd[0:7] sa[0:14] sd[0:7] 15 8 5 v 13 77 76 78 0.1 f 7 figure 3. typical connection diagram
ds271pp4 11 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 2.0 pin description 36 40 41 46 47 48 49 50 26 27 28 29 30 31 33 32 34 35 37 38 39 42 43 44 45 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 76 77 78 79 80 2 1 3 16 5 4 6 8 7 9 10 11 12 13 14 15 17 18 20 19 21 22 23 24 53 54 55 56 57 58 59 60 61 62 63 64 51 52 65 66 68 67 69 70 71 72 73 74 75 25 eedataout eesk eecs eedatain chipsel dmack2 dmack1 dmack0 dmarq2 dmarq1 dmarq0 sd15 sd14 sd13 sd12 dvdd2 dvss2 sd11 csout sd10 sd08 sa3 sa4 sa15 sa14 avss4 bstatus or hc1 txd + txd - avss1 avdd1 rxd - rxd + avss2 avdd2 test sleep xtal1 xtal2 res avss3 sa0 intrq2 intrq1 iocs16 intrq0 memcs16 sbhe sa1 sa2 intrq3 sa9 sa10 sa8 sa11 sa5 sa6 sa7 refresh sa19 sa18 sa17 dvdd3 dvss3 sa16 sd0 aen iow ior iochrd y sd1 sd5 sd4 sd3 sd2 dvss4 dvdd4 sd6 sd7 linkled or hc0 reset sa13 memw memr dvss1 dvdd1 elcs avss0 dvss1a sd09 sa12 dvss3a avdd3 lanled do- do+ di- di+ ci- ci+ CS8900A 100-pin tqfp (q) top view
12 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet isa bus interface sa[0:19] - system address bus, input pins 37-48, 50-54, 58-60. lower 20 bits of the 24-bit system address bus used to decode accesses to CS8900A i/o and memory space, and attached boot prom. sa0-sa15 are used for i/o read and write operations. sa0-sa19 are used in conjunction with external decode logic for memory read and write operations. sd[0:15] - system data bus, bi-directional with 3-state output pins 65-68, 71-74, 27-24, 21-18. bi-directional 16-bit system data bus used to transfer data between the CS8900A and the host. reset - reset, input pin 75. active-high asynchronous input used to reset the CS8900A. must be stable for at least 400 ns before the CS8900A recognizes the signal as a valid reset. aen - address enable, input pin 63. when test is high, this active-high input indicates to the CS8900A that the system dma controller has control of the isa bus. when aen is high, the CS8900A will not perform slave i/o space operations. when test is low, this pin becomes the shift clock input for the boundary scan test. aen should be inactive when performing an io or memory access and it should be active during a dma cycle. memr - memory read, input pin 29. active-low input indicates that the host is executing a memory read operation. memw - memory write, input pin 28. active-low input indicates that the host is executing a memory write operation. memcs16 - memory chip select 16-bit, open drain output pin 34. open-drain, active-low output generated by the CS8900A when it recognizes an address on the isa bus that corresponds to its assigned memory space (CS8900A must be in memory mode with the memorye bit (register 17, busctl, bit a) set for memcs16 to go active). 3-stated when not active. refresh - refresh, input pin 49. active-low input indicates to the CS8900A that a dram refresh cycle is in progress. when refresh is low, memr , memw , ior , iow , dmack0 , dmack1 , and dmack2 are ignored. ior - i/o read, input pin 61. when ior is low and a valid address is detected, the CS8900A outputs the contents of the selected 16-bit i/o register onto the system data bus. ior is ignored if refresh is low. iow - i/o write, input pin 62. when iow is low and a valid address is detected, the CS8900A writes the data on the system data bus into the selected 16-bit i/o register. iow is ignored if refresh is low.
ds271pp4 13 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet iocs16 - i/o chip select 16-bit, open drain output pin 33. open-drain, active-low output generated by the CS8900A when it recognizes an address on the isa bus that corresponds to its assigned i/o space. 3-stated when not active. iochrdy - i/o channel ready, open drain output pin 64. when driven low, this open-drain, active-high output extends i/o read and memory read cycles to the CS8900A. this output is functional when the iochrdye bit in the bus control register (register 17) is clear. this pin is always 3-stated when the iochrdye bit is set. sbhe - system bus high enable, input pin 36. active-low input indicates a data transfer on the high byte of the system data bus (sd8- sd15). after a hardware or a software reset, provide a high to low and then low to high transition on sbhe signal before any io or memory access is done to the CS8900A. intrq[0:3] - interrupt request, 3-state pins 30-32, 35. active-high output indicates the presence of an interrupt event. interrupt request goes low once the interrupt status queue (isq) is read as all 0 ? s. only one interrupt request output is used (one is selected during configuration). all non-selected interrupt request outputs are placed in a high-impedance state. (section 3.2 on page 17 and section 5.1 on page 78.) dmarq[0:2] - dma request, 3-state pins 11, 13, and 15. active-high, 3-stateable output used by the CS8900A to request a dma transfer. only one dma request output is used (one is selected during configuration). all non-selected dma request outputs are placed in a high-impedance state. dmack [0:2] - dma acknowledge, input pins 12, 14, and 16. active-low input indicates acknowledgment by the host of the corresponding dma request output. chipsel - chip select, input pin 7. active-low input generated by external latchable address bus decode logic when a valid memory address is present on the isa bus. if memory mode operation is not needed, chipsel should be tied low. the chipsel is ignored for io and dma mode of the CS8900A. eeprom and boot prom interface eesk - eeprom serial clock, pin 4. serial clock used to clock data into or out of the eeprom. eecs - eeprom chip select, pin 3. active-high output used to select the eeprom.
14 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet eedatain - eeprom data in, input internal weak pullup pin 6. serial input used to receive data from the eeprom. connects to the do pin on the eeprom. eedatain is also used to sense the presence of the eeprom. elcs - external logic chip select, internal weak pullup pin 2. bi-directional signal used to configure external latchable address (la) decode logic. if external la decode logic is not needed, elcs should be tied low. eedataout - eeprom data out,pin 5. serial output used to send data to the eeprom. connects to the di pin on the eeprom. when test is low, this pin becomes the output for the boundary scan test. csout - chip select for external boot prom, pin 17. active-low output used to select an external boot prom when the CS8900A decodes a valid boot prom memory address. 10base-t interface txd+/txd- - 10base-t transmit, differential output pair pins 87 and 88. differential output pair drives 10 mb/s manchester-encoded data to the 10base-t transmit pair. rxd+/rxd- - 10base-t receive, differential input pair pins 91 and 92. differential input pair receives 10 mb/s manchester-encoded data from the 10base-t receive pair. attachment unit interface (aui) do+/do- - aui data out, differential output pair pins 83 and 84. differential output pair drives 10 mb/s manchester-encoded data to the aui transmit pair. di+/di- - aui data in, differential input pair pins 79 and 80. differential input pair receives 10 mb/s manchester-encoded data from the aui receive pair. ci+/ci- - aui collision in, differential input pair pins 81 and 82. differential input pair connects to the aui collision pair. a collision is indicated by the presence of a 10 mhz 15% signal with duty cycle no worse than 60/40. general pins xtal[1:2] - crystal, input/output pins 97 and 98. a 20 mhz crystal should be connected across these pins. if a crystal is not used, a 20 mhz signal should be connected to xtal1 and xtal2 should be left open. (see section 7.3 on page 110 and section 7.7 on page 120.)
ds271pp4 15 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet sleep - hardware sleep, input internal weak pullup pin 77. active-low input used to enable the two hardware sleep modes: hardware suspend and hardware standby. (see section 3.7 on page 25.) linkled or hc0 - link good led or host controlled output 0, open drain output pin 99. when the hce0 bit of the self control register (register 15) is clear, this active-low output is low when the CS8900A detects the presence of valid link pulses. when the hc0e bit is set, the host may drive this pin low by setting the hcbo in the self control register. bstatus or hc1 - bus status or host controlled output 1, open drain output pin 78. when the hc1e bit of the self control register (register 15) is clear, this active-low output is low when receive activity causes an isa bus access. when the hc1e bit is set, the host may drive this pin low by setting the hcb1 in the self control register. lanled - lan activity led, open drain output pin 100. during normal operation, this active-low output goes low for 6 ms whenever there is a receive packet, a transmit packet, or a collision. during hardware standby mode, this output is driven low when the receiver detects network activity. test - test enable, input internal weak pullup pin 76. active-low input used to put the CS8900A in boundary scan test mode. for normal operation, this pin should be high. res - reference resistor, input pin 93. this input should be connected to a 4.99k ? 1% resistor needed for biasing of internal analog circuits. dvdd[1:4] - digital power, power pins 9, 22, 56, and 69. provides 5 v 5% power to the digital circuits of the CS8900A. dvss[1:4} and dvss1a, dvss3a - digital ground, ground pins 8, 10, 23, 55, 57, and 70. provides ground reference (0 v) to the digital circuits of the CS8900A. avdd[1:3] - analog power, power pins 90, 85, and 95. provides 5 v 5% power to the analog circuits of the CS8900A. avss[0:4] - analog ground, ground pins 1, 89, 86, 94, 96. provide ground reference (0 v) to the analog circuits of the CS8900A.
16 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 3.0 functional description 3.1 overview during normal operation, the CS8900A performs two basic functions: ethernet packet transmission and reception. before transmission or reception is possible, the CS8900A must be configured. 3.1.1 configuration the CS8900A must be configured for packet trans- mission and reception at power-up or reset. various parameters must be written into its internal config- uration and control registers such as memory base address; ethernet physical address; what frame types to receive; and which media interface to use. configuration data can either be written to the CS8900A by the host (across the isa bus), or load- ed automatically from an external eeprom. oper- ation can begin after configuration is complete. section 3.3 on page 18 and section 3.4 on page 20 describe the configuration process in detail. section 4.4 on page 46 provides a detailed descrip- tion of the bits in the configuration and control registers. 3.1.2 packet transmission packet transmission occurs in two phases. in the first phase, the host moves the ethernet frame into the CS8900A ? s buffer memory. the first phase be- gins with the host issuing a transmit command. this informs the CS8900A that a frame is to be transmitted and tells the chip when to start trans- mission (i.e. after 5, 381, 1021 or all bytes have been transferred) and how the frame should be sent (i.e. with or without crc, with or without pad bits, etc.). the host follows the transmit command with the transmit length, indicating how much buffer space is required. when buffer space is available, the host writes the ethernet frame into the CS8900A ? s internal memory, either as a mem- ory or i/o space operation. in the second phase of transmission, the CS8900A converts the frame into an ethernet packet then transmits it onto the network. the second phase be- gins with the CS8900A transmitting the preamble and start-of-frame delimiter as soon as the proper number of bytes has been transferred into its trans- mit buffer (5, 381, 1021 bytes or full frame, de- pending on configuration). the preamble and start- of-frame delimiter are followed by the destination address, source address, length field and llc data (all supplied by the host). if the frame is less than 64 bytes, including crc, the CS8900A adds pad bits if configured to do so. finally, the CS8900A appends the proper 32-bit crc value. the section 5.7 on page 98 provides a detailed de- scription of packet transmission. 3.1.3 packet reception like packet transmission, packet reception occurs in two phases. in the first phase, the CS8900A re- ceives an ethernet packet and stores it in on-chip memory. the first phase of packet reception begins with the receive frame passing through the analog front end and manchester decoder where manches- ter data is converted to nrz data. next, the pream- ble and start-of-frame delimiter are stripped off and the receive frame is sent through the address filter. if the frame ? s destination address matches the criteria programmed into the address filter, the packet is stored in the CS8900A ? s internal memo- ry. the CS8900A then checks the crc, and de- pending on the configuration, informs the processor that a frame has been received. in the second phase, the host transfers the receive frame across the isa bus and into host memory. receive frames can be transferred as memory space operations, i/o space operations, or as dma operations using host dma. also, the CS8900A provides the capability to switch between memory or i/o operation and dma operation by using auto-switch dma and streamtransfer. the section 5.2 on page 78 through section 5.6 on page 95 provide a detailed description of packet re- ception.
ds271pp4 17 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 3.2 isa bus interface the CS8900A provides a direct interface to isa buses running at clock rates from 8 to 11 mhz. its on-chip bus drivers are capable of delivering 24 ma of drive current, allowing the CS8900A to drive the isa bus directly, without added external "glue logic". the CS8900A is optimized for 16-bit data trans- fers, operating in either memory space, i/o space, or as a dma slave. note that isa-bus operation below 8 mhz should use the CS8900A ? s receive dma mode to mini- mize missed frames. see section 5.4 on page 89 for a description of receive dma operation. 3.2.1 memory mode operation when configured for memory mode operation, the CS8900A ? s internal registers and frame buffers are mapped into a contiguous 4-kbyte block of host memory, providing the host with direct access to the CS8900A ? s internal registers and frame buff- ers. the host initiates read operations by driving the memr pin low and write operations by driv- ing the memw pin low. for additional information about memory mode, see section 4.9 on page 73. 3.2.2 i/o mode operation when configured for i/o mode operation, the CS8900A is accessed through eight, 16-bit i/o ports that are mapped into sixteen contiguous i/o locations in the host system ? s i/o space. i/o mode is the default configuration for the CS8900A and is always enabled. for an i/o read or write operation, the aen pin must be low, and the 16-bit i/o address on the isa system address bus (sa0 - sa15) must match the address space of the CS8900A. for a read, ior must be low, and for a write, iow must be low. for additional information about i/o mode, see section 4.10 on page 75. 3.2.3 interrupt request signals the CS8900A has four interrupt request output pins that can be connected directly to any four of the isa bus interrupt request signals. only one in- terrupt output is used at a time. it is selected during initialization by writing the interrupt number (0 to 3) into packetpage memory base + 0022h. unused interrupt request pins are placed in a high-imped- ance state. the selected interrupt request pin goes high when an enabled interrupt is triggered. the pin goes low after the interrupt status queue (isq) is read as all 0 ? s (see section 5.1 on page 78 for a description of the isq). table 1 presents one possible way of connecting the interrupt request pins to the isa bus that utiliz- es commonly available interrupts and facilitates board layout. 3.2.4 dma signals the CS8900A interfaces directly to the host dma controller to provide dma transfers of receive frames from CS8900A memory to host memory. the CS8900A has three pairs of dma pins that can be connected directly to the three 16-bit dma channels of the isa bus. only one dma channel is used at a time. it is selected during initialization by writing the number of the desired channel (0, 1 or 2) into packetpage memory base + 0024h. unused dma pins are placed in a high-impedance state. the selected dma request pin goes high when the CS8900A has received frames to transfer to the host memory via dma. if the dmaburst bit (reg- ister 17, busctl, bit b) is clear, the pin goes low after the dma operation is complete. if the CS8900A interrupt request pin isa bus interrupt packetpage base + 0022h intrq3 (pin 35) irq5 0003h intrq0 (pin 32) irq10 0000h intrq1 (pin 31) irq11 0001h intrq2 (pin 30) irq12 0002h table 1. interrupt assignments
18 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet dmaburst bit is set, the pin goes low 32 s after the start of a dma transfer. the dma pin pairs are arranged on the CS8900A to facilitate board layout. crystal recommends the configuration in table 2 when connecting these pins to the isa bus. for a description of dma mode, see section 5.4 on page 89. 3.3 reset and initialization 3.3.1 reset seven different conditions cause the CS8900A to reset its internal registers and circuits. 3.3.1.1 external reset, or isa reset there is a chip-wide reset whenever the reset pin is high for at least 400 ns. during a chip-wide reset, all circuitry and registers in the CS8900A are reset. 3.3.1.2 power-up reset when power is applied, the CS8900A maintains re- set until the voltage at the supply pins reaches ap- proximately 2.5 v. the CS8900A comes out of reset once vcc is greater than approximately 2.5 v and the crystal oscillator has stabilized. 3.3.1.3 power-down reset if the supply voltage drops below approximately 2.5 v, there is a chip-wide reset. the CS8900A comes out of reset once the power supply returns to a level greater than approximately 2.5 v and the crystal oscillator has stabilized. 3.3.1.4 eeprom reset there is a chip-wide reset if an eeprom check- sum error is detected (see section 3.4 on page 20). 3.3.1.5 software initiated reset there is a chip-wide reset whenever the reset bit (register 15, selfctl, bit 6) is set. 3.3.1.6 hardware (hw) standby or suspend the CS8900A goes though a chip-wide reset when- ever it enters or exits either hw standby mode or hw suspend mode (see section 3.7 on page 25 for more information about hw standby and sus- pend). 3.3.1.7 software (sw) suspend whenever the CS8900A enters sw suspend mode, all registers and circuits are reset except for the isa i/o base address register (located at packetpage base + 0020h) and the selfctl register (register 15). upon exit, there is a chip-wide reset (see section 3.7 on page 25 for more information about sw suspend). 3.3.2 allowing time for reset operation after a reset, the CS8900A goes through a self con- figuration. this includes calibrating on-chip analog circuitry, and reading eeprom for validity and configuration. time required for the reset calibra- tion is typically 10 ms. software drivers should not access registers internal to the CS8900A during this time. when calibration is done, bit initd in the self status register (register 16) is set indicat- ing that initialization is complete, and the sibusy bit in the same register is cleared indicating the ee- prom is no longer being read or programmed. 3.3.3 bus reset considerations the CS8900A reads 3000h from iobase+0ah after the reset, until the software writes a non-zero value at iobase+0ah. the 3000h value can be used as part of the CS8900A signature when the system scans for the CS8900A. see section 4.10 on page 75. CS8900A dma signal (pin #) isa dma signal packetpage base + 0024h dmarq0 (pin 15) drq5 0000h dmack0 (pin 16) dack5 dmarq1 (pin 13) drq6 0001h dmack1 (pin 14) dack6 dmarq2 (pin 11) drq7 0002h dmack2 (pin 12) dack7 table 2. dma assignments
ds271pp4 19 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet after a reset, the isa bus outputs intrx and dmarqx are 3-stated, thus avoiding any interrupt or dma channel conflicts on the isa bus at power- up time. 3.3.4 initialization after each reset (except eeprom reset), the CS8900A checks the sense of the eedatain pin to see if an external eeprom is present. if eedi is high, an eeprom is present and the CS8900A au- tomatically loads the configuration data stored in the eeprom into its internal registers (see next section). if eedi is low, an eeprom is not present and the CS8900A comes out of reset with the default configuration shown in table 3. a low-cost serial eeprom can be used to store configuration information that is automatically loaded into the CS8900A after each reset (except eeprom reset). the use of an eeprom is op- tional. the CS8900A operates with any of six standard eeprom ? s shown in table 4. packetpage address register contents register descriptions 0020h 0300h i/o base address* 0022h xxxx xxxx xxxx x100 interrupt number 0024h xxxx xxxx xxxx xx11 dma channel 0026h 0000h dma start of frame offset 0028h x000h dma frame count 002ah 0000h dma byte count 002ch xxx0 0000h memory base address 0030h xxx0 0000h boot prom base address 0034h xxx0 0000h boot prom address mask 0102h 0003h register 3 - rxcfg 0104h 0005h register 5 - rxctl 0106h 0007h register 7 - txcfg 0108h 0009h register 9 - txcmd 010ah 000bh register b - bufcfg 010ch undefined reserved 010eh undefined reserved 0110h undefined reserved 0112h 00013h register 13 - linectl 0114h 0015h register 15 - selfctl 0116h 0017h register 17 - busctl 0118h 0019h register 19 - testctl * i/o base address is unaffected by software suspend mode. table 3. d efault configuration eeprom type size (16-bit words) ? c46 (non-sequential) 64 ? cs46 (sequential) 64 ? c56 (non-sequential) 128 ? cs56 (sequential) 128 ? c66 (non-sequential) 256 ? cs66 (sequential) 256 table 4. supported eeprom types
20 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 3.4 configurations with eeprom 3.4.1 eeprom interface the interface to the eeprom consists of the four signals shown in table 5. 3.4.2 eeprom memory organization if an eeprom is used to store initial configuration information for the CS8900A, the eeprom is or- ganized in one or more blocks of 16-bit words. the first block in eeprom, referred to as the configu- ration block, is used to configure the CS8900A af- ter reset. an example of a typical configuration block is shown in table 6. additional blocks con- taining user data may be stored in the eeprom. however, the configuration block must always start at address 00h and be stored in contiguous memory locations. 3.4.3 reset configuration block the first block in eeprom, referred to as the re- set configuration block, is used to automatically program the CS8900A with an initial configuration after a reset. additional user data may also be stored in the eeprom if space is available. the additional data are stored as 16-bit words and can occupy any eeprom address space beginning im- mediately after the end of the reset configuration block up to address 7fh, depending on eeprom size. this additional data can only be accessed through software control (refer to section 3.5 on page 23 for more information on accessing the ee- prom). address space 80h to afh is reserved. 3.4.3.1 reset configuration block structure the reset configuration block is a block of contig- uous 16-bit words starting at eeprom address 00h. it can be divided into three logical sections: a header, one or more groups of configuration data words, and a checksum value. all of the words in the reset configuration block are read sequential- ly by the CS8900A after each reset, starting with the header and ending with the checksum. each group of configuration data is used to program a packetpage register (or set of packetpage registers in some cases) with an initial non-default value. 3.4.3.2 reset configuration block header the header (first word of the block located at ee- prom address 00h) specifies the type of ee- prom used, whether or not a reset configuration block is present, and if so, how many bytes of con- figuration data are stored in the reset configura- tion block. 3.4.3.3 determining the eeprom type the lsb of the high byte of the header indicates the type of eeprom attached: sequential or non- sequential. an lsb of 0 (xxxx-xxx0) indicates a sequential eeprom. an lsb of 1 (xxxx- xxx1) indicates a non-sequential eeprom. the CS8900A works equally well with either type of eeprom. the CS8900A will automatically gen- erate sequential addresses while reading the reset configuration block if a non-sequential eeprom is used. 3.4.3.4 checking eeprom for presence of reset configuration block the read-out of either a binary 101x-xxx0 or 101x-xxx1 (x = do not care) from the high byte of the header indicates the presence of configura- tion data. any other readout value terminates ini- tialization from the eeprom. if an eeprom is attached but not used for configuration, crystal rec- ommends that the high byte of the first word be programmed with 00h in order to ensure that the CS8900A pin (pin #) CS8900A function eeprom pin eecs (pin 3) eeprom chip select chip select eesk (pin 4) 1 mhz eeprom serial clock output clock eedo (pin 5) eeprom data out (data to eeprom) data in eedi (pin 6) eeprom data in (data from eeprom) data out table 5. eeprom interface
ds271pp4 21 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet CS8900A will not attempt to read configuration data from the eeprom. 3.4.3.5 determining number of bytes in the reset configuration block the low byte of the reset configuration block header is known as the link byte. the value of the link byte represents the number of bytes of config- uration data in the reset configuration block. the two bytes used for the header are excluded when calculating the link byte value. for example, a reset configuration block header of a104h indicates a non-sequential eeprom pro- grammed with a reset configuration block con- taining 4 bytes of configuration data. this reset configuration block occupies 6 bytes (3 words) of eeprom space (2 bytes for the header and 4 bytes of configuration data). 3.4.4 groups of configuration data configuration data are arranged as groups of words. each group contains one or more words of data that are to be loaded into packetpage registers. word address value description first word in data block 00h a120h configuration block header. the high byte, a1h, indicates a ? c46 eeprom is attached. the link byte, 20h, indicates the number of bytes to be used in this block of configuration data. first group of words 01h 2020h group header for first group of words. three words to be loaded, beginning at 0020h in packetpage memory. 02h 0300h i/o base address 03h 0003h interrupt number 04h 0001h dma channel number second group of words 05h 502ch group header for second group of words. six words to be loaded, beginning at 002ch in packetpage memory. 06h e000h memory base address - low word 07 000fh memory base address - high word 08h 0000h boot prom base address - low word 09h 000dh boot prom base address - high word 0ah c000h boot prom address mask - low word 0bh 000fh boot prom address mask - high word third group of words 0ch 2158h group header for third group of words. three words to be loaded, beginning at 0158 in packetpage memory. 0dh 0010h individual address - octet 0 and 1 0eh 0000h individual address - octet 2 and 3 0fh 0000h individual address - octet 4 and 5 checksum value 10h 2800h the high byte, 28h, is the checksum value. in this example, the check- sum includes word addresses 00h through 0fh. the hexadecimal sum of the bytes is d8h, resulting in a 2 ? s complement of 28h. the low byte, 00h, provides a pad to the word boundary. * ffffh is a special code indicating that there are no more words in the eeprom. table 6. eeprom configuration block example
22 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet the first word of each group is referred to as the group header. the group header indicates the number of words in the group and the address of the packetpage register into which the first data word in the group is to be loaded. any remaining words in the group are stored in successive packetpage registers. 3.4.4.1 group header bits f through c of the group header specify the number of words in each group that are to be trans- ferred to packetpage registers (see figure 4). this value is two less than the total number of words in the group, including the group header. for exam- ple, if bits f through c contain 0001, there are three words in the group (a group header and two words of configuration data). bits 8 through 0 of the group header specify a 9- bit packetpage address. this address defines the packetpage register that will be loaded with the first word of configuration data from the group. bits b though 9 of the group header are forced to 0, restricting the destination address range to the first 512 bytes of packetpage memory. figure 4 shows the format of the group header. 3.4.5 reset configuration block checksum a checksum is stored in the high byte position of the word immediately following the last group of data in the reset configuration block. (the ee- prom address of the checksum value can be deter- mined by dividing the value stored in the link byte by two). the checksum value is the 2 ? s comple- ment of the 8-bit sum (any carry out of eighth bit is ignored) of all the bytes in the reset configuration block, excluding the checksum byte. this sum in- cludes the reset configuration block header at ad- dress 00h. since the checksum is calculated as the 2 ? s complement of the sum of all preceding bytes in the reset configuration block, a total of 0 should result when the checksum value is added to the sum of the previous bytes. 3.4.6 eeprom example table 6 shows an example of a reset configuration block stored in a c46 eeprom. note that little- endian word ordering is used, i.e., the least signifi- cant word of a multiword datum is located at the lowest address. 3.4.7 eeprom read-out if the eedi pin is asserted high at the end of reset, the CS8900A reads the first word of eeprom data by: 1) asserting eecs 2) clocking out a read-register-00h command on eedo (eesk provides a 1mhz serial clock signal) 3) clocking the data in on eedi. if the eedi pin is low at the end of the reset signal, the CS8900A does not perform an eeprom read- out (uses its default configuration). 3.4.7.1 determining eeprom size the CS8900A determines the size of the eeprom by checking the sense of eedi on the tenth rising edge of eesk. if eedi is low, the eeprom is a 10 3 2 5 4 76 first word of a group of words 98 ba dc f e number of words in group 0 0 9-bit packetpage address 0 figure 4. group header
ds271pp4 23 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet ? c46 or ? cs46. if eedi is high, the eeprom is a ? c56, ? cs56, ? c66, or ? cs66. 3.4.7.2 loading configuration data the CS8900A reads in the first word from the ee- prom to determine if configuration data is con- tained in the eeprom. if configuration data is not stored in the eeprom, the CS8900A terminates initialization from eeprom and operates using its default configuration (see table 3). if configura- tion data is stored in eeprom, the CS8900A auto- matically loads all configuration data stored in the reset configuration block into its internal pack- etpage registers. 3.4.8 eeprom read-out completion once all the configuration data are transferred to the appropriate packetpage registers, the CS8900A performs a checksum calculation to verify the re- set configuration blocks data are valid. if the re- sulting total is 0, the read-out is considered valid. otherwise, the CS8900A initiates a partial reset to restore the default configuration. if the read-out is valid, the eepromok bit (reg- ister 16, selfst, bit a) is set. eepromok is cleared if a checksum error is detected. in this case, the CS8900A performs a partial reset and is re- stored to its default. once initialization is complete (configuration loaded from eeprom or reset to default configuration) the initd bit is set (register 16, selfst, bit 7). 3.5 programming the eeprom after initialization, the host can access the ee- prom through the CS8900A by writing one of seven commands to the eeprom command regis- ter (packetpage base + 0040h). figure 5 shows the format of the eeprom command register. 3.5.1 eeprom commands the seven commands used to access the eeprom are: read, write, erase, erase/write enable, erase/write disable, erase-all, and write-all. they are described in table 7. 3.5.2 eeprom command execution during the execution of a command, the two op- code bits, followed by the six bits of address (for a ? c46 or ? cs46) or eight bits of address (for a ? c56, ? cs56, ? c66 or ? cs66), are shifted out of the CS8900A, into the eeprom. if the command is a write, the data in the eeprom data register (packetpage base + 0042h) follows. if the com- mand is a read, the data in the specified eeprom f x e x d x c x b x elsel op1 op0 a98 ad5 ad4 54 76 ad7 ad6 10 32 ad1 ad0 ad3 ad2 ad5 - ad0 used with ? c46 and ? cs46 ad7 - ad0 used with ? c56, ? cs56, ? c66 and ? cs66 figure 5. eeprom command register format bit name description [f:b] reserved [a] elsel external logic select: when clear, the eecs pin is used to select the eeprom. when set, the elcs pin is used to select the external la decode circuit. [9:8] op1, op0 opcode: indicates what command is being executed (see next section). [7:0] ad7 to ad0 eeprom address: address of eeprom word being accessed.
24 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet location is written into the eeprom data register. if the command is an erase or erase-all, no data is transferred to or from the eeprom data register. before issuing any command, the host must wait for the sibusy bit (register 16, selfst, bit 8) to clear. after each command has been issued, the host must wait again for sibusy to clear. 3.5.3 enabling access to the eeprom the erase/write enable command provides protec- tion from accidental writes to the eeprom. the host must write an erase/write enable command before it attempts to write to or erase any eeprom memory location. once the host has finished alter- ing the contents of the eeprom, it must write an erase/write disable command to prevent unwant- ed modification of the eeprom. 3.5.4 writing and erasing the eeprom to write data to the eeprom, the host must exe- cute the following series of commands: 1) issue an erase/write enable command . 2) load the data into the eeprom data register. 3) issue a write command. 4) issue an erase/write disable command. during the erase command, the CS8900A writes ffh to the specified eeprom location. during the erase-all command, the CS8900A writes ffh to all locations. 3.6 boot prom operation the CS8900A supports an optional boot prom used to store code for remote booting from a net- work server. 3.6.1 accessing the boot prom to retrieve the data stored in the boot prom, the host issues a read command to the boot prom as a memory space access. the CS8900A decodes the command and drives the csout pin low, causing the data stored in the boot prom to be shifted into the bus transceiver. the bus transceiver then drives the data out onto the isa bus. 3.6.2 configuring the CS8900A for boot prom operation figure 6 shows how the CS8900A should be con- nected to the boot prom and ? 245 driver. to con- figure the CS8900A ? s internal registers for boot prom operation, the boot prom base address must be loaded into the boot prom base address register (packetpage base + 0030h) and the boot prom address mask must be loaded into the command opcode (bits 9,8) eeprom address (bits 7 to 0) data eeprom type execution time read register 1,0 word address yes all 25 s write register 0,1 word address yes all 10 ms erase register 1.1 word address no all 10 ms erase/write enable 0,0 xx11-xxxx no ? cs46, ? c46 9 s 11xx-xxxx no ? cs56, ? c56, ? cs66, ? c66 9 s erase/write disable 0,0 0,0 xx00-xxxx no ? cs46, ? c46 9 s 00xx-xxxx no ? cs56, ? c56, ? cs66, ? c66 9 s erase-all registers 0,0 0,0 xx10-xxxx no ? cs46, ? c46 10 ms 10xx-xxxx no ? cs56, ? c56, ? cs66, ? c66 9 s write-all register 0,0 0,0 xx01-xxxx yes ? cs46, ? c46 10 ms 01xx-xxxx yes ? cs56, ? c56, ? cs66, ? c66 10 ms table 7. eeprom commands
ds271pp4 25 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet bootprom address mask register (packetpage base + 0034h). the boot prom base address pro- vides the starting location in host memory where the boot prom is mapped. the boot prom ad- dress mask indicates the size of the attached boot prom and is limited to 4-kbyte increments. the lower 12 bits of the address mask are ignored and should be 000h. in the eeprom example shown in table 6, the boot prom starting address is d0000h and the address mask is fc000h. this configuration de- scribes a 16-kbyte (128 kbit) prom mapped into host memory from d0000h to d3fffh. 3.7 low-power modes for power-sensitive applications, the CS8900A supports three low-power modes: hardware stand- by, hardware suspend, and software suspend. all three low-power modes are controlled through the selfctl register (register 15). see also section 4.4.4 on page 48. an internal reset occurs when the CS8900A comes out of any suspend or standby mode. after a reset (internal or external), the CS8900A goes through a self configuration. this includes calibrating on- chip analog circuitry, and reading eeprom for va- lidity and configuration. when the calibration is done, bit initd in register 16 (self status register) is set indicating that initialization is complete, and the sibusy bit in the same register is cleared (in- dicating that the eeprom is no longer being read or programmed. time required for the reset calibra- tion is typically 10 ms. software drivers should not access registers internal to CS8900A during this time. 3.7.1 hardware standby hardware (hw) standby is designed for use in sys- tems, such as portable pc ? s, that may be temporari- ly disconnected from the 10base-t cable. it allows the system to conserve power while the lan is not in use, and then automatically restore ethernet operation once the cable is reconnected. in hw standby mode, all analog and digital cir- cuitry in the CS8900A is turned off, except for the 10base-t receiver which remains active to listen for link activity. if link activity is detected, the lanled pin is driven low, providing an indica- tion to the host that the network connection is ac- tive. the host can then activate the CS8900A by deasserting the sleep pin. during this mode, all isa bus accesses are ignored. to enter hw standby mode, the sleep pin must be low and the hwsleepe bit (register 15, self- ctl, bit 9) and the hwstandbye bit (register 15, selfctl, bit a) must be set. when the CS8900A enters hw standby, all registers and circuits are re- set except for the selfctl register. upon exit from hw standby, the CS8900A performs a complete reset, and then goes through normal initialization. 3.7.2 hardware suspend during hardware suspend mode, the CS8900A uses the least amount of current of the three low- power modes. all internal circuits are turned off and the CS8900A ? s core is electronically isolated from the rest of the system. accesses from the isa bus and ethernet activity are both ignored. hw suspend mode is entered by driving the sleep pin low and setting the hwsleepe bit (register 15, selfctl, bit 9) while the hwstand- bye bit (register 15, selfctl, bit a) is clear. to oe dir b1 . . . b8 a1 . . . a8 74ls245 sd(0:7) isa bus sa(0:14) 27c256 ce oe 20 22 19 CS8900A csout (pin 17) figure 6. boot prom connection diagram
26 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet exit from this mode, the sleep pin must be driven high. upon exit, the CS8900A performs a complete reset, and then goes through a normal initialization procedure. 3.7.3 software suspend software (sw) suspend mode can be used to con- serve power in applications, like adapter cards, that do not have power management circuitry available. during this mode, all internal circuits are shut off except the i/o base address register (packetpage base + 0020h) and the selfctl register (register 15). to enter sw suspend mode, the host must set the swsuspend bit (register 15, selfctl, bit 8). to exit sw suspend, the host must write to the CS8900A ? s assigned i/o space (the write is only used to wake the CS8900A, the write itself is ig- nored). upon exit, the CS8900A performs a com- plete reset, and then goes through a normal initialization procedure. any hardware reset takes the chip out of any sleep mode. table 8 summarizes the operation of the three low- power modes. CS8900A configuration CS8900A operation sleep (pin 77) hwstandbye (selfctl, bit a) hwsleepe (selfctl, bit 9) swsuspend (selfctl, bit 8) link activity low 1 1 n/a not present hw standby mode: 10base-t receiver listens for link activity low 1 1 n/a present hw standby mode: lanled low low 0 1 n/a n/a hw suspend mode low to high n/a 1 0 n/a CS8900A resets and goes through initialization high n/a n/a 0 n/a not in low-power mode high n/a n/a n/a sw suspend mode low n/a 0 1 n/a sw suspend mode low n/a 0 0 n/a not in low-power mode notes: 1. both hw and hw suspend take precedence over sw suspend. table 8. low-power mode operation
ds271pp4 27 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 3.8 led outputs the CS8900A provides three output pins that can be used to control leds or external logic. 3.8.0.1 lanled lanled goes low whenever the CS8900A trans- mits or receives a frame, or when it detects a colli- sion. lanled remains low until there has been no activity for 6 ms (i.e. each transmission, reception, or collision produces a pulse lasting a minimum of 6 ms). 3.8.0.2 linkled or hc0 linkled or hc0 can be controlled by either the CS8900A or the host. when controlled by the CS8900A, linkled is low whenever the CS8900A receives valid 10base-t link pulses. to configure this pin for CS8900A control, the hc0e bit (register 15, selfctl, bit c) must be clear. when controlled by the host, linkled is low whenever the hcb0 bit (register 15, selfctl, bit e) is set. to configure it for host control, the hc0e bit must be set. table 9 summarizes this operation. 3.8.0.3 bstatus or hc1 bstatus or hc1 can be controlled by either the CS8900A or the host. when controlled by the CS8900A, bstatus is low whenever the host reads the rxevent register (packetpage base + 0124h), signaling the transfer of a receive frame across the isa bus. to configure this pin for CS8900A control, the hc1e bit (register 15, self- ctl, bit d) must be clear. when controlled by the host, bstatus is low whenever the hcb1 bit (register 15, selfctl, bit f) is set. to configure it for host control, hc1e must be set. table 10 sum- marizes this operation. 3.8.1 led connection each led output is capable of sinking 10 ma to drive an led directly through a series resistor. the output voltage of each pin is less than 0.4 v when the pin is low. figure 7 shows a typical led cir- cuit. 3.9 media access control 3.9.1 overview the CS8900A ? s ethernet media access control (mac) engine is fully compliant with the ieee 802.3 ethernet standard (iso/iec 8802-3, 1993). it handles all aspects of ethernet frame transmission and reception, including: collision detection, pre- amble generation and detection, and crc genera- hc0e (bit c) hcb0 (bit e) pin function 0n/a pin configured as linkled : output is low when valid 10base-t link pulses are detected. output is high if valid link pulses are not detected 10 pin configured as hc0 : output is high 11 pin configured as hc0 : output is low table 9. linkled /hc0 pin operation hc1e (bit d) hcb1 (bit f) pin function 0n/a pin configured as bstatus : output is low when a receive frame begins trans- fer across the isa bus. output is high otherwise 10 pin configured as hc1 : output is high 11 pin configured as hc1 : output is low table 10. bstatus /hci pin operation +5v lanled linkled figure 7. led connection diagram
28 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet tion and test. programmable mac features include automatic retransmission on collision, and padding of transmitted frames. figure 8 shows how the mac engine interfaces to other CS8900A functions. on the host side, it inter- faces to the CS8900A ? s internal data/address/con- trol bus. on the network side, it interfaces to the internal manchester encoder/decoder (endec). the primary functions of the mac are: frame en- capsulation and decapsulation; error detection and handling; and, media access management. 3.9.2 frame encapsulation and decapsulation the CS8900A ? s mac engine automatically as- sembles transmit packets and disassembles receive packets. it also determines if transmit and receive frames are of legal minimum size. 3.9.2.1 transmission once the proper number of bytes have been trans- ferred to the CS8900A ? s memory (either 5, 381, 1021 bytes, or full frame), and providing that ac- cess to the network is permitted, the mac automat- ically transmits the 7-byte preamble (1010101b...), followed by the start-of-frame delimiter (sfd, 10101011b), and then the serialized frame data. it then transmits the frame check sequence (fcs). the data after the sfd and before the fcs (desti- nation address, source address, length, and data field) is supplied by the host. fcs generation by the CS8900A may be disabled by setting the inhibit- crc bit (register 9, txcmd, bit c). figure 9 shows the ethernet frame format. 3.9.2.2 reception the mac receives the incoming packet as a serial stream of nrz data from the manchester encod- er/decoder. it begins by checking for the sfd. once the sfd is detected, the mac assumes all subsequent bits are frame data. it reads the da and compares it to the criteria programmed into the ad- dress filter (see section 5.3 on page 86 for a de- scription of address filtering). if the da passes the address filter, the frame is loaded into the CS8900A ? s memory. if the buffercrc bit (regis- ter 3, rxcfg, bit b) is set, the received fcs is also loaded into memory. once the entire packet has been received, the mac validates the fcs. if an er- ror is detected, the crcerror bit (register 4, rx- event, bit c) is set. 3.9.2.3 enforcing minimum frame size the mac provides minimum frame size enforce- 802.3 mac engine encoder/ decoder & pll led logic CS8900A internal bus 10base-t & aui figure 8. mac interface 1 byte up to 7 bytes 6 bytes 6 bytes 2 bytes llc data pad fcs 4 bytes preamble frame length min 64 bytes max 1518 bytes alternating 1s / 0s sfd da sa sfd = start of frame delimiter da = destination address sa = source address direction of transmission frame packet llc = logical link control fcs = frame check sequence (also called cyclic redundancy check, or crc) length field figure 9. ethernet frame format
ds271pp4 29 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet ment of both transmit and receive packets. when the txpaddis bit (register 9, txcmd, bit d) is clear, transmit frames will be padded with addition- al bits to ensure that the receiving station receives a legal frame (64 bytes, including crc). when tx- paddis is set, the CS8900A will not add pad bits and will transmit frames less that 64 bytes. if a frame is received that is less than 64 bytes (includ- ing crc), the runt bit (register 4, rxevent, bit d) will be set indicating the arrival of an illegal frame. 3.9.3 transmit error detection and handling the mac engine monitors ethernet activity and reports and recovers from a number of error condi- tions. for transmission, the mac reports the fol- lowing errors in the txevent register (register 8) and bufevent register (register c): 3.9.3.1 loss of carrier whenever the CS8900A is transmitting on the aui port, it expects to see its own transmission "looped back" to its receiver. if it is unable to monitor its transmission after the end of the preamble, the mac reports a loss-of-carrier error by setting the loss-of-crs bit (register 8, txevent, bit 6). if the loss-of-crsie bit (register 7, txcfg, bit 6) is set, the host will be interrupted. 3.9.3.2 sqe error after the end of transmission on the aui port, the mac expects to see a collision within 64 bit times. if no collision is detected, the sqeerror bit (regis- ter 8, txevent, bit 7) is set. if the sqeerrorie bit is set (register 7, txcfg, bit 7), the host is interrupt- ed. an sqe error may indicate a fault on the aui cable or a faulty transceiver (it is assumed that the attached transceiver supports this function). 3.9.3.3 out-of-window (late) collision if a collision is detected after the first 512 bits have been transmitted, the mac reports a late collision by setting the out-of-window bit (register 8, tx- event, bit 9). the mac then forces a bad crc and terminates the transmission. if the out-of-window- ie bit (register 7, txcfg, bit 9) is set, the host is interrupted. a late collision may indicate an illegal network configuration. 3.9.3.4 jabber error if a transmission continues longer than about 26 ms, the mac disables the transmitter and sets the jabber bit (register 8, txevent, bit a). the output of the transmitter returns to idle and remains there until the host issues a new transmit com- mand. if the jabberie bit (register 7, txcfg, bit a) is set, the host is interrupted. a jabber condition indicates that there may be something wrong with the CS8900A transmit function. to prevent possi- ble network faults, the host should clear the trans- mit buffer. possible options include: reset the chip with either software or hardware re- set (see section 3.3 on page 18). issue a force transmit command by setting the force bit (register 9, txcmd, bit 8). issue a transmit command with the txlength field set to zero. 3.9.3.5 transmit collision the mac counts the number of times an individual packet must be retransmitted due to network colli- sions. the collision count is stored in bits b through e of the txevent register (register 8). if the packet collides 16 times, transmission of that packet is terminated and the 16coll bit (register 8, txevent, bit f) is set. if the 16collie bit (register 7, txcfg, bit f) is set, the host will be interrupted on the 16th collision. a running count of transmit collisions is recorded in the txcol register. 3.9.3.6 transmit underrun if the CS8900A starts transmission of a packet but runs out of data before reaching the end of frame, the txunderrun bit (register c, bufevent, bit 9) is set. the mac then forces a bad crc and termi- nates the transmission. if the txunderrunie bit
30 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet (register b, bufcfg, bit 9) is set, the host is inter- rupted. 3.9.4 receive error detection and handling the following receive errors are reported in the rx- event register (register 4): 3.9.4.1 crc error if a frame is received with a bad crc, the crcer- ror bit (register 4, rxevent, bit c) is set. if the crcerrora bit (register 5, rxctl, bit c) is set, the frame will be buffered by CS8900A. if the crcerrorie bit (register 3, rxcfg. bit c) is set, the host is interrupted. 3.9.4.2 runt frame if a frame is received that is shorter than 64 bytes, the runt bit (register 4, rxevent, bit d) is set. if the runta bit (register 5, rxctl, bit d) is set, the frame will still be buffered by CS8900A. if the runtie bit (register 3, rxcfg. bit d) is set, the host is interrupted. 3.9.4.3 extra data if a frame is received that is longer than 1518 bytes, the extradata bit (register 4, rxevent, bit e) is set. if the extradataa bit (register 5, rxctl, bit e) is set, the first 1518 bytes of the frame will still be buffered by CS8900A. if the extradataie bit (reg- ister 3, rxcfg. bit e) is set, the host is interrupted. 3.9.4.4 dribble bits and alignment error under normal operating conditions, the mac may detect up to 7 additional bits after the last full byte of a receive packet. these bits, known as dribble bits, are ignored. if dribble bits are detected, the dribblebit bit (register 4, rxevent, bit 7) is set. if both the dribblebits bit and crcerror bit (register 4, rxevent, bit c) are set at the same time, an alignment error has occurred. 3.9.5 media access management the ethernet network topology is a single shared medium with several attached stations. the ether- net protocol is designed to allow each station equal access to the network at any given time. any node can attempt to gain access to the network by first completing a deferral process (described below) af- ter the last network activity, and then transmitting a packet that will be received by all other stations. if two nodes transmit simultaneously, a collision oc- curs and the colliding packets are corrupted. two primary tasks of the mac are to avoid network col- lisions, and then recover from them when they oc- cur. in addition, when the CS8900A is using the aui, the mac must support the sqe test function described in section 7.2.4.6 of the ethernet stan- dard. 3.9.5.1 collision avoidance the mac continually monitors network traffic by checking for the presence of carrier activity (carrier activity is indicated by the assertion of the internal carrier sense signal generated by the endec). if carrier activity is detected, the network is assumed busy and the mac must wait until the current packet is finished before attempting transmission. the CS8900A supports two schemes for determin- ing when to initiate transmission: two-part defer- ral, and simple deferral. selection of the deferral scheme is determined by the 2-partdefdis bit (register 13, linectl, bit d). if the 2-partdefdis bit is clear, the mac uses a two-part deferral pro- cess defined in section 4.2.3.2.1 of the ethernet standard (iso/iec 8802-3, 1993). if the 2-partdef- dis bit is set, the mac uses a simplified deferral scheme. both schemes are described below: 3.9.5.2 two-part deferral in the two-part deferral process, the 9.6 s inter packet gap (ipg) timer is started whenever the in- ternal carrier sense signal is deasserted. if activity is detected during the first 6.4 s of the ipg timer, the timer is reset and then restarted once the activi- ty has stopped. if there is no activity during the first 6.4 s of the ipg timer, the ipg timer is allowed to time out (even if network activity is detected during
ds271pp4 31 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet the final 3.2 s). the mac then begins transmis- sion if a transmit packet is ready and if it is not in backoff (backoff is described later in this section). if no transmit packet is pending, the mac contin- ues to monitor the network. if activity is detected before a transmit frame is ready, the mac defers to the transmitting station and resumes monitoring the network. the two-part deferral scheme was developed to prevent the possibility of the ipg being shortened due to a temporary loss of carrier. figure 10 dia- grams the two-part deferral process. 3.9.5.3 simple deferral in the simple deferral scheme, the ipg timer is started whenever carrier sense is deasserted. once the ipg timer is finished (after 9.6 s), if a transmit frame is pending and if the mac is not in backoff, transmission begins the 9.6 s ipg). if no transmit packet is pending, the mac continues to monitor the network. if activity is detected before a transmit frame is ready, the mac defers to the transmitting station and resumes monitoring the network. fig- ure 11 diagrams the simple deferral process. 3.9.5.4 collision resolution if a collision is detected while the CS8900A is transmitting, the mac responds in one of three ways depending on whether it is a normal collision (within the first 512 bits of transmission) or a late collision (after the first 512 bits of transmission): 3.9.5.5 normal collisions if a collision is detected before the end of the pre- amble and sfd, the mac finishes the preamble and sfd, transmits the jam sequence (32-bit pat- tern of all 0 ? s), and then initiates backoff. if a col- lision is detected after the transmission of the preamble and sfd but before 512 bit times, the mac immediately terminates transmission, trans- mits the jam sequence, and then initiates backoff. in either case, if the onecoll bit (register 9, txc- md, bit 9) is clear, the mac will attempt to trans- mit a packet a total of 16 times (the initial attempt plus 15 retransmissions) due to normal collisions. on the 16th collision, it sets the 16coll bit (register 8, txevent, bit f) and discards the pack- et. if the onecoll bit is set, the mac discards the packet without attempting any retransmission. transmit frame start monitoring network activity ipg timer = 6.4 s? network active? network active? start ipg timer network active? yes no yes yes yes no no no no wait 3.2 s yes tx frame ready and not in backoff? figure 10. two-part deferral
32 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 3.9.5.6 late collisions if a collision is detected after the first 512 bits have been transmitted, the mac immediately terminates transmission, transmits the jam sequence, discards the packet, and sets the out-of-window bit (regis- ter 8, txevent, bit 9). the CS8900A does not ini- tiate backoff or attempt to retransmit the frame. for additional information about late collisions, see out-of-window error in this section. 3.9.5.7 backoff after the mac has completed transmitting the jam sequence, it must wait, or "back off", before at- tempting to transmit again. the amount of time it must wait is determined by one of two backoff al- gorithms: the standard backoff algorithm (iso/iec 4.2.3.2.5) or the modified backoff algo- rithm. the host selects which algorithm through the modbackoffe bit (register 13, linectl, bit b). 3.9.5.8 standard backoff the standard backoff algorithm, also called the "truncated binary exponential backoff", is de- scribed by the equation: 0 r 2 k where r (a random integer) is the number of slot times the mac must wait (1 slot time = 512 bit times), and k is the smaller of n or 10, where n is the number of retransmission attempts. 3.9.5.9 modified backoff the modified backoff is described by the equation: 0 r 2 k where r (a random integer) is the number of slot times the mac must wait, and k is 3 for n < 3 and k is the smaller of n or 10 for n 3, where n is the number of retransmission attempts. the advantage of the modified backoff algorithm over the standard backoff algorithm is that it re- duces the possibility of multiple collisions on the first three retries. the disadvantage is that it ex- tends the maximum time needed to gain access to the network for the first three retries. the host may choose to disable the backoff algo- rithm altogether by setting the disablebackoff bit (register 19, testctl, bit b). when disabled, the CS8900A only waits the 9.6 s ipg time before starting transmission. 3.9.5.10 sqe test if the CS8900A is transmitting on the aui, the ex- ternal transceiver should generate an sqe test sig- nal on the ci+/ci- pair following each transmission. the sqe test is a 10 mhz signal lasting 5 to 15 bit times and starting within 0.6 to t x fra m e ready and not i n b ac k off? transmit frame start monitoring network activity network active? network active? yes no yes no no yes wait 9.6 s figure 11. simple deferral
ds271pp4 33 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 1.6 s after the end of transmission. during this pe- riod, the CS8900A ignores receive carrier activity (see sqe error in this section for more informa- tion). 3.10 encoder/decoder (endec) the CS8900A ? s integrated encoder/decoder (en- dec) circuit is compliant with the relevant por- tions of section 7 of the ethernet standard (iso/iec 8802-3, 1993). its primary functions include: manchester encoding of transmit data; informing the mac when valid receive data is present (carri- er detection); and, recovering the clock and nrz data from incoming manchester-encoded data. figure 12 provides a block diagram of the endec and how it interfaces to the mac, aui and 10base-t transceiver. 3.10.1 encoder the encoder converts nrz data from the mac and a 20 mhz transmit clock signal into a serial stream of manchester data. the transmit clock is produced by an on-chip oscillator circuit that is driven by either an external 20 mhz quartz crystal or a ttl-level cmos clock input. if a cmos in- put is used, the clock should be 20 mhz 0.01% with a duty cycle between 40% and 60%. the spec- ifications for the crystal are described in section 7.7 on page 120. the encoded signal is routed to either the 10base-t transceiver or aui, depending on configuration. 3.10.2 carrier detection the internal carrier detection circuit informs the mac that valid receive data is present by asserting the internal carrier sense signal as soon it detects a valid bit pattern (1010b or 0101b for 10base-t, and 1b or 0b for aui). during normal packet recep- tion, carrier sense remains asserted while the frame is being received, and is deasserted 1.3 to 2.3 bit times after the last low-to-high transition of the end-of-frame (eof) sequence. whenever the re- ceiver is idle (no receive activity), carrier sense is deasserted. the crs bit (register 14, linest, bit e) reports the state of the carrier sense signal. 3.10.3 clock and data recovery when the receiver is idle, the phase-lock loop (pll) is locked to the internal clock signal. the as- sertion of the carrier sense signal interrupts the pll. when it restarts, it locks on the incoming da- ta. the receive clock is then compared to the in- coming data at the bit cell center and any phase difference is corrected. the pll remains locked as long as the receiver input signal is valid. once the pll has locked on the incoming data, the endec converts the manchester data to nrz and passes the decoded data and the recovered clock to the mac for further processing. encoder carrier detector decoder & pll rx mux tx mux rxsql auisql rx tx auirx auitx auicol clock carrier sense rx clk rx nrz txclk tx nrz ten port select collision mac endec 10base-t transceiver aui figure 12. endec
34 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 3.10.4 interface selection physical interface selection is determined by aui- only bit (bit 8) and the autoaui/10bt (bit 9) in the linectl register (register 13). table 11 de- scribes the possible configurations. 3.10.4.1 10base-t only when configured for 10base-t only operation, the 10base-t transceiver and its interface to the endec are active, and the aui is powered down. 3.10.4.2 aui only when configured for aui-only operation, the aui and its interface to the endec are active, and the 10base-t transceiver is powered down. 3.10.4.3 auto-select in auto-select mode, the CS8900A automatically selects the 10base-t interface and powers down the aui if valid packets or link pulses are detected by the 10base-t receiver. if valid packets and link pulses are not detected, the CS8900A selects the aui. whenever the aui is selected, the 10base-t receiver remains active to listen for link pulses or packets. if 10base-t activity is detect- ed, the CS8900A switches back to 10base-t. 3.11 10base-t transceiver the CS8900A includes an integrated 10base-t transceiver that is compliant with the relevant por- tions of section 14 of the ethernet standard (iso/iec 8802-3, 1993). it includes all analog and digital circuitry needed to interface the CS8900A directly to a simple isolation transformer (see section 7.5 on page 119 for a connection diagram). figure 13 provides a block diagram of the 10base-t transceiver. 3.11.1 10base-t filters the CS8900A ? s 10base-t transceiver includes integrated low-pass transmit and receive filters, eliminating the need for external filters or a fil- ter/transformer hybrid. on-chip filters are gm/c im- plementations of fifth-order butterworth low-pass filters. internal tuning circuits keep the gm/c ratio tightly controlled, even when large temperature, supply, and ic process variations occur. the nom- inal 3 db cutoff frequency of the filters is 16 mhz, and the nominal attenuation at 30 mhz (3rd har- monic) is -27 db. auionly (bit 8) autoaui/10bt (bit 9) physical interface 0010base-t only 1 n/a aui only 0 1 auto-select table 11. interface selection rxsql rx tx link pulse detector tx pre- distortion rx squelch rx comparator tx filters filter tuning rx filters tx drivers rxd- rxd + txd- txd+ endec linkok (to mac) 10base-t transceiver figure 13. 10base-t transceiver
ds271pp4 35 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 3.11.2 transmitter when configured for 10base-t operation, manchester encoded data from the endec is fed into the transmitter ? s predistortion circuit where initial wave shaping and preequalization is per- formed. the output of the predistortion circuit is fed into the transmit filter where final wave shaping occurs and unwanted noise is removed. the signal then passes to the differential driver where it is am- plified and driven out of the txd+/txd- pins. in the absence of transmit packets, the transmitter generates link pulses in accordance with section 14.2.1.1. of the ethernet standard. transmitted link pulses are positive pulses, one bit time wide, typi- cally generated at a rate of one every 16 ms. the 16 ms timer starts whenever the transmitter com- pletes an end-of-frame (eof) sequence. thus, there is a link pulse 16 ms after an eof unless there is another transmitted packet. figure 14 diagrams the operation of the link pulse generator. if no link pulses are being received on the receiver, the 10base-t transmitter is internally forced to an inactive state unless bit disablelt in register 19 (test control register) is set to one. 3.11.3 receiver the 10base-t receive section consists of the re- ceive filter, squelch circuit, polarity detection and correction circuit, and link pulse detector. 3.11.3.1 squelch circuit the 10base-t squelch circuit determines when valid data is present on the rxd+/rxd- pair. in- coming signals passing through the receive filter are tested by the squelch circuit. any signal with amplitude less than the squelch threshold (either positive or negative, depending on polarity) is re- jected. 3.11.3.2 extended range the CS8900A supports an extended range feature that reduces the 10base-t receive squelch thresh- old by approximately 6 db. this allows the CS8900A to operate with 10base-t cables that are longer than 100 meters (100 meters is the max- imum length specified by the ethernet standard). the exact additional distance depends on the qual- ity of the cable and the amount of electromagnetic noise in the surrounding environment. to activate this feature, the host must set the lorxsquelch bit (register 13, linectl, bit e). 3.11.4 link pulse detection to prevent disruption of network operation due to a faulty link segment, the CS8900A continually monitors the 10base-t receive pair (rxd+/ rxd-) for packets and link pulses. after each packet or link pulse is received, an internal link- loss timer is started. as long as a packet or link pulse is received before the link-loss timer finish- es (between 25 and 150 ms), the CS8900A main- tains normal operation. if no receive activity is detected, the CS8900A disables packet transmis- sion to prevent "blind" transmissions onto the net- work (link pulses are still sent while packet transmission is disabled). to reactivate transmis- sion, the receiver must detect a single packet (the packet itself is ignored), or two link pulses separat- time link pulse link pulse 16ms 16ms less than 16ms packet packet figure 14. link pulse transmission
36 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet ed by more than 2 to 7 ms and no more than 25 to 150 ms (see section 7.4 on page 112 for 10base- t timing). the state of the link segment is reported in the linkok bit (register 14, linest, bit 7). if the hc0e bit (register 15, selfctl, bit d) is clear, it is also indicated by the output of the linkled pin. if the link is "good", the linkok bit is set and the linkled pin is driven low. if the link is "bad" the linkok bit is clear and the linkled pin is high. to disable this feature, the host must set the disablelt bit (register 19, testctl, bit 7). if disablelt is set, the CS8900A will transmit and receive packets independent of the link segment. 3.11.5 receive polarity detection and correction the CS8900A automatically checks the polarity of the receive half of the twisted pair cable. if the po- larity is correct, the polarityok bit (register 14, linest, bit c) is set. if the polarity is reversed, the polarityok bit is clear. if the polaritydis bit (reg- ister 13, linectl, bit c) is clear, the CS8900A au- tomatically corrects a reversal. if the polaritydis bit is set, the CS8900A does not correct a reversal. the polarityok bit and the polaritydis bit are in- dependent. to detect a reversed pair, the receiver examines re- ceived link pulses and the end-of-frame (eof) se- quence of incoming packets. if it detects at least one reversed link pulse and at least four frames in a row with negative polarity after the eof, the re- ceive pair is considered reversed. any data re- ceived before the correction of the reversal is ignored. 3.11.6 collision detection if half-duplex operation is selected (register 19, bit e, fdx), the CS8900A detects a 10base-t collision whenever the receiver and transmitter are active simultaneously. when a collision is present, the collision detection circuit informs the mac by asserting the internal collision signal (see section 3.9 on page 27 for collision handling). 3.12 attachment unit interface (aui) the CS8900A attachment unit interface (aui) provides a direct interface to external 10base2, 10base5, and 10base-fl ethernet transceivers. it is fully compliant with section 7 of the ethernet standard (iso/iec 8802-3), and as such, is capable of driving a full 50-meter aui cable. the aui consists of three pairs of signals: data out (do+/do-), data in (di+/di-), and collision in (ci+/ci-). to select the aui, the host should set the aui bit (register 13, linectl, bit 8). the aui can also be selected automatically as described in the previous section (section 3.10.4 on page 34). figure 15 provides a block diagram of the aui. (for a connection diagram, see section 7.6 on page 120). 3.12.1 aui transmitter the aui transmitter is a differential driver de- signed to drive a 78 ? cable. it accepts data from the endec and transmits it directly on the do+/do- pins. after transmission has started, the CS8900A expects to see the packet "looped-back" (or echoed) to the receiver, causing the carrier sense signal to be asserted. this carrier sense presence indicates that the transmit signal is getting through to the transceiver. if the carrier sense sig- nal remains deasserted throughout the transmis- di+ di- do+ do- endec cl+ cl- collision detect auicol (to mac) auirx auisql auitx aui - + - + figure 15. aui
ds271pp4 37 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet sion, or if the carrier sense signal is deasserted before the end of the transmission, there is a loss- of-carrier error and the loss-of-crs bit (register 8, txevent, bit 6) is set. 3.12.2 aui receiver the aui receiver is a differential pair circuit that connects directly to the di+/di- pins. it is designed to distinguish between transient noise pulses and incoming ethernet packets. incoming packets with proper amplitude and pulse width are passed on to the endec section, while unwanted noise is re- jected. 3.12.3 collision detection the aui collision circuit is a differential pair re- ceiver that detects the presence of collision signals on the ci+/ci- pins. the collision signal is generat- ed by an external ethernet transceiver whenever a collision is detected on the ethernet segment. (sec- tion 7.3.1.2 of iso/iec 8802-3, 1993, defines the collision signal as a 10 mhz 15% signal with a duty cycle no worse than 60/40). when a collision is present, the aui collision circuit informs the mac by asserting the internal collision signal. 3.13 external clock oscillator a 20-mhz quartz crystal or cmos clock input is required by the CS8900A. if a cmos clock input is used, it should be connected the to xtal1 pin, with the xtal2 pin left open. the clock signal should be 20 mhz 0.01% with a duty cycle be- tween 40% and 60%. the specifications for the crystal are described in section 7.7 on page 120.
38 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.0 packetpage architecture 4.1 packetpage overview the CS8900A architecture is based on a unique, highly-efficient method of accessing internal regis- ters and buffer memory known as packetpage. packetpage provides a unified way of controlling the CS8900A in memory or i/o space that mini- mizes cpu overhead and simplifies software. it provides a flexible set of performance features and configuration options, allowing designers to devel- op ethernet circuits that meet their particular sys- tem requirements. 4.1.1 integrated memory central to the CS8900A architecture is a 4-kbyte page of integrated ram known as packetpage memory. packetpage memory is used for tempo- rary storage of transmit and receive frames, and for internal registers. access to this memory is done directly, through memory space operations (section 4.9 on page 73), or indirectly, through i/o space operations (section 4.10 on page 75). in most cases, memory mode will provide the best overall performance, because isa memory opera- tions require fewer cycles than i/o operations. i/o mode is the CS8900A ? s default configuration and is used when memory space is not available or when special operations are required (e.g. waking the CS8900A from the software suspend state re- quires the host to write to the CS8900A ? s assigned i/o space). the user-accessible portion of packetpage memory is organized into the following six sections: 4.1.2 bus interface registers the bus interface registers are used to configure the CS8900A ? s isa-bus interface and to map the CS8900A into the host system ? s i/o and memory space. most of these registers are written only dur- ing initialization, remaining unchanged while the CS8900A is in normal operating mode. the excep- tions to this are the dma registers which are mod- ified continually whenever the CS8900A is using dma. these registers are described in more detail in section 4.3 on page 41. 4.1.3 status and control registers the status and control registers are the primary means of controlling and getting status of the CS8900A. they are described in more detail in section 4.4 on page 46. 4.1.4 initiate transmit registers the txcmd/txlength registers are used to initiate ethernet frame transmission. these registers are described in more detail in section 4.5 on page 70. (see section 5.7 on page 98 for a description of frame transmission.) 4.1.5 address filter registers the filter registers store the individual address fil- ter and logical address filter used by the destina- tion address (da) filter. these registers are described in more detail in section 4.6 on page 71. for a description of the da filter, see section 5.3 on page 86. 4.1.6 receive and transmit frame locations the receive and transmit frame packetpage loca- tions are used to transfer ethernet frames to and from the host. the host simply writes to and reads from these locations and internal buffer memory is dynamically allocated between transmit and re- ceive as needed. this provides more efficient use of buffer memory and better overall network per- formance. as a result of this dynamic allocation, only one receive frame (starting at packetpage base + 0400h) and one transmit frame (starting at pack- packetpage address contents 0000h - 0045h bus interface registers 0100h - 013fh status and control registers 0140h - 014fh initiate transmit registers 0150h - 015dh address filter registers 0400h receive frame location 0a00h transmit frame location
ds271pp4 39 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet etpage base + 0a00h) are directly accessible. see section 4.7 on page 72. 4.2 packetpage memory map table 12 shows the CS8900A packetpage memory address map: s packetpage address # of bytes type description cross reference bus interface registers 0000h 4 read-only product identification code section 4.3 on page 41 0004h 28 - reserved note 2 0020h 2 read/write i/o base address section 4.3 on page 41, section 4.7 on page 72 0022h 2 read/write interrupt number (0,1,2,or 3) section 3.2 on page 17, section 4.3 on page 41 0024h 2 read/write dma channel number (0, 1, or 2) section 3.2 on page 17, section 4.3 on page 41 0026h 2 read-only dma start of frame section 4.3 on page 41, section 5.4 on page 89 0028h 2 read-only dma frame count (12 bits) sections section 4.3 on page 41, ? receive dma ? 002ah 2 read-only rxdma byte count section 4.3 on page 41, section 5.4 on page 89 002ch 4 read/write memory base address register (20 bit) section 4.3 on page 41, section 4.9 on page 73 0030h 4 read/write boot prom base address section 3.6 on page 24, section 4.3 on page 41 0034h 4 read/write boot prom address mask section 3.6 on page 24, section 4.3 on page 41 0038h 8 - reserved note 2 0040h 2 read/write eeprom command section 3.5 on page 23, section 4.3 on page 41 0042h 2 read/write eeprom data section 3.5 on page 23, section 4.3 on page 41 0044h 12 - reserved note 2 0050h 2 read only received frame byte counter section 4.3 on page 41, section 5.2.9 on page 86 0052h 174 - reserved note 2 status and control registers 0100h 32 read/write configuration & control registers (2 bytes per regiseter) section 4.4 on page 46 0120h 32 read-only status & event registers (2 bytes per register) section 4.4 on page 46 0140h 4 - reserved note 2 initiate transmit registers notes: 1. all registers are accessed as words only. 2. read operation from the reserved location provides undefined data. writing to a reserved location or undefined bits may result in unpredictable operation of the CS8900A. table 12. packetpage memory address map
40 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 0144h 2 write-only txcmd (transmit command) section 4.5 on page 70, section 5.7 on page 98 0146h 2 write-only txlength (transmit length) section 4.5 on page 70, section 5.7 on page 98 0148h 8 - reserved note 2 address filter registers 0150h 8 read/write logical address filter (hash table) section 4.6 on page 71, section 5.3 on page 86 0158h 6 read/write individual address section 4.6 on page 71, section 5.3 on page 86 015eh 674 - reserved note 2 frame location 0400h 2 read-only rxstatus (receive status) section 4.7 on page 72, section 5.2 on page 78 0402h 2 read-only rxlength (receive length, in bytes) section 4.7 on page 72, section 5.2 on page 78 0404h - read-only receive frame location section 4.7 on page 72, section 5.2 on page 78 0a00 - write-only transmit frame location section 4.7 on page 72, section 5.7 on page 98 packetpage address # of bytes type description cross reference notes: 1. all registers are accessed as words only. 2. read operation from the reserved location provides undefined data. writing to a reserved location or undefined bits may result in unpredictable operation of the CS8900A. table 12. packetpage memory address map (continued)
ds271pp4 41 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.3 bus interface registers 4.3.1 product identification code (read only, address: packetpage base + 0000h) the product identification code register is located in the first four bytes of the packetpage (0000h to 0003h). the register contains a unique 32-bit product id code that identifies the chip as a CS8900A. the host can use this num- ber to determine which software driver to load and to check which features are available. reset value is: 0000 1110 0110 0011 0000 0000 000x xxxx the x xxxx codes for the CS8900A are: rev b: 0 0111 rev c: 0 1000 rev d: 0 1001 4.3.2 i/o base address (read/write, address: packetpage base + 0020h) the i/o base address register describes the base address for the sixteen contiguous locations in the host system ? s i/o space, which are used to access the packetpage registers. see section 4.10 on page 75. the default location is 0300h. after reset, if no eeprom is found by the CS8900A, then the register has the following initial state. if an eeprom is found, then the register ? s initial value may be set by the eeprom. see section 3.3 on page 18. reset value is: 0000 0011 0000 0000 address 0000h address 0001h address 0002h address 00003h first byte of eisa registration number for crystal semiconductor second byte of eisa registration number for crys- tal semiconductor first 8 bits of product id number last 3 bits of the product id number (5 ? x ? bits are the revi- sion number) address 0021h address 0020h most significant byte of i/o base address least significant byte of i/o base address
42 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.3.3 interrupt number (read/write, address: packetpage base + 0022h) the interrupt number register defines the interrupt pin selected by the CS8900A. in a typical application the follow- ing bus signals are tied to the following pins: see section 3.2 on page 17. after reset, if no eeprom is found by the CS8900A, then the register has the following initial state, which corre- sponds to placing all the intrq pins in a high-impedance state. if an eeprom is found, then the register ? s initial value may be set by the eeprom. see section 3.3 on page 18. reset value is: xxxx xxxx xxxx x100 4.3.4 dma channel number (read/write, address: packetpage base + 0024h) the dma channel register defines the dma pins selected by the CS8900A. in the typical application, the following bus signals are tied to the following pins: see section 3.2 on page 17 and section 5.4 on page 89. after reset, if no eeprom is found by the CS8900A, then the register has the following initial state which corre- sponds to setting all dmrq pins to high-impedance. if a eeprom is found, then the register ? s initial value may be set by the eeprom. see section 3.3 on page 18. reset value is: xxxx xxxx xxxx xx11 address 0023h address 0022h 00h interrupt number assignment: 0000 0000b= pin intrq0 0000 0001b= pin intrq1 0000 0010b= pin intrq2 0000 0011b= pin intrq3 0000 01xxb= all intrq pins high-impedance bus signal typical pin connection irq5 intrq3 irq10 intrq0 irq11 intrq1 irq12 intrq2 address 0025h address 0024h 00h dma channel assignment: 0000 0000b= pin dmrq0 and dmack0 0000 0001b= pin dmrq1 and dmack1 0000 0010b= pin dmrq2 and dmack2 0000 0011b= all dmrq pins high-impedance bus signal typical pin connection drq5 dack5 dmrq0 dmack0 drq6 dack6 dmrq1 dmack1 drq7 dack7 dmrq2 dmack2
ds271pp4 43 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.3.5 dma start of frame (read only, address: packetpage base + 0026h) the dma start of frame register contains a 16-bit value which defines the offset from the dma base address to the start of the most recently transferred received frame. see section 5.4 on page 89. reset value is: 0000 0000 0000 0000 4.3.6 dma frame count (read only, address: packetpage base + 0028h) the lower 12 bits of the dma frame count register define the number of valid frames transferred via dma since the last readout of this register. the upper 4 bits are reserved. see section 5.4 on page 89. reset value is: xxxx 0000 0000 0000 4.3.7 rxdma byte count (read only, address: packetpage base + 002ah) the rxdma byte count register describes the valid number of bytes dmaed since the last readout. see section 5.4 on page 89. reset value is: 0000 0000 0000 0000 4.3.8 memory base address (read/write, address: packetpage base + 002ch) memory base address: the lower three bytes (002ch, 002dh, and 002eh) are used for the 20-bit memory base address. the upper three nibbles are reserved. after reset, if no eeprom is found by the CS8900A, then the register has the following initial state. if an eeprom is found, then the register ? s initial value may be set by the eeprom. see section 3.3 on page 18. reset value is: xxxx xxxx xxxx 0000 0000 0000 0000 0000 address 0027h address 0026h most significant byte of offset value least significant byte of offset value address 0029h address 0028h most significant byte of frame count (most-significant nibble always 0h) least significant byte of frame count address 002bh address 002ah most significant byte of byte count least significant byte of byte count address 002fh address 002eh address 002dh address 002ch reserved the most significant nibble of memory base address. the high-order nibble is reserved. contains portion of memory base address. the least significant byte of the memory base address.
44 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.3.9 boot prom base address (read/write, address: packetpage base + 0030h) the lower three bytes (0030h, 0031h, and 0032h) of the boot prom base address register are used for the 20-bit boot prom base address. the upper three nibbles are reserved. see section 3.6 on page 24. after reset, if no eeprom is found by the CS8900A, then the register has the following initial state. if an eeprom is found, then the register ? s initial value may be set by the eeprom. see section 3.3 on page 18. reset value is: xxxx xxxx xxxx 0000 0000 0000 0000 0000 4.3.10 boot prom address mask (read/write, address: packetpage base + 0034h) the boot prom address mask register indicates the size of the attached boot prom and is limited to 4k bit incre- ments. the lower 12 bits of the address mask are ignored, and should be 000h. the next lowest-order bits describe the size of the prom. the upper three nibbles are reserved. for example: see section 3.6 on page 24. after reset, if no eeprom is found by the CS8900A, then the register has the following initial state. if an eeprom is found, then the register ? s initial value may be set by the eeprom. see section 3.3 on page 18. reset value is: xxxx xxxx xxxx 0000 0000 0000 0000 0000 address 0033h address 0032h address 0031h address 0030h reserved the most significant nibble of boot prom base address. the high-order nibble is reserved. contains portion of boot prom base address. the least significant byte of the boot prom base address. address 0037h address 0036h address 0035h address 0034h reserved the most significant nibble of boot prom mask address. the high-order nibble is reserved. contains portion of boot prom mask address. the lower-order nibble must be written as 0h. the least significant byte of the boot prom mask address. must be written as 00h. size of boot prom register value 4k bits xxxx xxxx xxxx 1111 1111 0000 0000 0000 8k bits xxxx xxxx xxxx 1111 1110 0000 0000 0000 16k bits xxxx xxxx xxxx 1111 1100 0000 0000 0000
ds271pp4 45 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.3.11 eeprom command (read/write, address: packetpage base + 0040h) this register is used to control the reading, writing and erasing of the eeprom. see section 3.5. add7-add0 address of the eeprom word being accessed. ob1,ob0 indicates the opcode of the command being executed. see table 7. elsel external logic select: when clear, the eecs pin is used to select the eeprom. when set, the elcs pin is used to select the external la decode circuit. reserved reserved and must be written as 0. reset value is: xxxx xxxx xxxx xxxx 4.3.12 eeprom data (read/write, address: packetpage base + 0042h) this register contains the word being written to, or read from, the eeprom. see section 3.5 on page 23. reset value is: xxxx xxxx xxxx xxxx 4.3.13 receive frame byte counter (read only, address: packetpage base + 0050h) this register contains the count of the total number bytes received in the current received frame. this count contin- uously increments as more bytes in this frame are received. see section 5.2.9 on page 86. reset value is: xxxx xxxx xxxx xxxx 76543210 add7 to add0 fedcba9 8 reserved elsel ob1 ob0 address 0043h address 0042h most significant byte of the eeprom data. least significant byte of the eeprom data. address 0051h address 0050h most significant byte of the byte count. least significant byte of the byte count.
46 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.4 status and control registers the status and control registers are the primary registers used to control and check the status of the CS8900A. they are organized into two groups: configuration/control registers and status/event registers. all status and control registers are 16- bit words as shown in figure 16. bit 0 indicates whether it is a configuration/control register (bit 0 = 1) or a status/event register (bit 0 = 0). bits 0 through 5 provide an internal address code that describes the exact function of the register. bits 6 through f are the actual configuration/con- trol and status/event bits. 4.4.1 configuration and control registers configuration and control registers are used to set- up the following: how frames will be transmitted and received; which frames will be transmitted and received; which events will cause interrupts to the host processor; and, how the ethernet physical interface will be configured. these registers are read/write and are designated by odd numbers (e.g. register 1, register 3, etc.). the transmit command register (txcmd) is a special type of register. it appears in two separate locations in the packetpage memory map. the first location, packetpage base + 0108h, is within the block of configuration/control registers and is read-only. the second location, packetpage base + 0144h, is where the actual transmit commands are issued and is write-only. see section 4.4.4 on page 48 (register 9) and section 5.7 on page 98 for a more detailed description of the txcmd register. 4.4.2 status and event registers status and event registers report the status of trans- mitted and received frames, as well as information about the configuration of the CS8900A. they are read-only and are designated by even numbers (e.g. register 2, register 4, etc.). the interrupt status queue (isq) is a special type of status/event register. it is located at packetpage base + 0120h and is the first register the host reads when responding to an interrupt. a more detailed description of the isq can be found in section 5.1 on page 78. three 10-bit counters are included with the status and event registers. rxmiss counts missed re- ceive frames, txcol counts transmit collisions, and tdr is a time domain reflectometer useful in locating cable faults. the following sections con- tain more information about these counters. table 13 provides a summary of packetpage reg- ister types. 4.4.3 status and control bit definitions this section provides a description of the special bit types used in the status and control registers. 1 0 32 54 76 10 register bits 1 = control/configuration 0 = status/event internal address (bits 0 - 5) 16-bit register word bit number 98 ba dc f e figure 16. status and control register format
ds271pp4 47 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet section 4.4.4 on page 48 provides a detailed de- scription of the bits in each register. 4.4.3.1 act-once bits there are four bits that cause the CS8900A to take a certain action only once when set. these "act- once" bits are: skip_1 (register 3, rxcfg, bit 6), reset (register 15, selfctl, bit 6), resetrxd- ma (register 17, busctl, bit 6), and swint-x (register b, bufcfg, bit 6). to cause the action again, the host must set the bit again. act-once bits are always read as clear. 4.4.3.2 temporal bits temporal bits are bits that are set and cleared by the CS8900A without intervention of the host proces- sor. this includes all status bits in the three status registers (register 14, linest; register 16, selfst; and, register 18, busst), the rxdest bit (register c, bufevent, bit f), and the rx128 bit (register c, bufevent, bit b). like all event bits, rxdest and rx128 are cleared when read by the host. 4.4.3.3 interrupt enable bits and events interrupt enable bits end with the suffix ie and are located in three configuration registers: rxcfg (register 3), txcfg (register 7), and bufcfg (register b). each interrupt enable bit corresponds to a specific event. if an interrupt enable bit is set and its corresponding event occurs, the CS8900A generates an interrupt to the host processor. the bits that report when various events occur are located in three event registers and two counters. the event registers are rxevent (register 4), tx- event (register 8), and bufevent (register c). the counters are rxmiss (register 10) and txcol (register 12). each interrupt enable bit and its as- sociated event are identified in table 14. an event bit will be set whenever the specified event happens, whether or not the associated inter- rupt enable bit is set. all event registers are cleared upon read-out by the host. 4.4.3.4 accept bits there are nine accept bits located in the rxctl register (register 5), each of which is followed by the suffix a. accept bits indicate which types of frames will be accepted by the CS8900A. (a frame is said to be "accepted" by the CS8900A when the frame data are placed in either on-chip memory, or in host memory by dma.) four of these bits have corresponding interrupt enable (ie) bits. an ac- cept bit and an interrupt enable bit are independent suffix type description comments cmd read/write command: written once per frame to initiate transmit. cfg read/write configuration: written at setup and used to determine what frames will be transmitted and received and what events will cause interrupts. ctl read/write control: written at setup and used to determine what frames will be transmitted and received and how the physi- cal interface will be configured. event read-only event: reports the status of transmitted and received frames. cleared when read st read-only status: reports information about the configuration of the CS8900A. read-only counters: counts missed receive frames and collisions. provides time domain for locating coax cable faults. cleared when read table 13. packetpage register types
48 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet operations. it is possible to set either, neither, or both bits. the four corresponding pairs of bits are: if one of the above interrupt enable bits is set and the corresponding accept bit is clear, the CS8900A generates an interrupt when the associated receive event occurs, but then does not accept the receive frame (the length of the receive frame is set to ze- ro). the other five accept bits in rxctl are used for destination address filtering (see section 5.3 on page 86). the accept mechanism is explained in more detail in section 5.2 on page 78. 4.4.4 status and control register summary the table on the following page (table 15) pro- vides a summary of the status and control regis- ters. section 4.4.4 on page 48 gives a detailed description of each status and control register. interrupt enable bit (register name) event bit or counter (register name) extradataie (rxcfg) extradata (rxevent) runtie (rxcfg) runt (rxevent) crcerrorie (rxcfg) crcerror (rxevent) rxokie (rxcfg) rxok (rxevent) 16collie (txcfg) 16coll (txevent) anycollie (txcfg) ? number-of tx-collisions ? counter is incremented (txevent) jabberie (txcfg) jabber (txevent) out-of-windowie (txcfg) out-of-window (txevent) txokie (txcfg) txok (txevent) sqeerrorie (txcfg) sqeerror (txevent) loss-of-crsie (txcfg) loss-of-crs (txevent) missovfloie (bufcfg) rxmiss counter over- flows past 1ffh txcolovfloie (bufcfg) txcol counter overflows past 1ffh rxdestie (bufcfg) rxdest (bufevent) rx128ie (bufcfg) rx128 (bufevent) rxmissie (bufcfg) rxmiss (bufevent) txunderrunie (bufcfg) txunderrun (bufevent) rdy4txie (bufcfg) rdy4tx (bufevent) rxdmaie (bufcfg) rxdmaframe (bufevent) table 14. interrupt enable bits and events ie bit in rxcfg a bit in rxctl extradataie extradataa runtie runta crcerrorie crcerrora rxokie rxoka
ds271pp4 49 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet control and configuration bits register fedcba9 876number (offset) name reserved (register contents undefined) 1 extra dataie runtie crc errorie buffer crc autorx dmae rxdma only rxokie streame skip_1 3 (0102h) rxcfg extra dataa runta crc errora broad casta individ uala multi casta rxoka promis cuousa iahash a 5 (0104h) rxctl 16colli e anycollie jab berie out-of- windowie txokie sqerro- rie loss-of- crsie 7 (0106h) txcfg txpad- dis inhibit- crc onecoll force txstart 9 (0108h) txcmd rxd- estie miss ovfloie txcol ovfloie rx128ie rxmis- sie txunder- runie rdy4txi e rxd- maie swint-x b (010ah) bufcfg reserved (register contents undefined) d-11 lorx squelch 2-part defdis polarity dis mod backoffe autoaui/ 10bt auionly ser txon ser rxon 13 (0112h) line ctl hcb1 hcb0 hc1e hc0e hwstan dbye hw sleepe sw sus- pend reset 15 (0114h) selfctl enabl e irq rxdma size ioch rdye dma burst memo- rye usesa dmaex- tend reset rxdma 17 (0116) busctl fdx disable backoff auiloop endec loop disable lt 19 (0118) te s t c t l reserved (register contents undefined) 1b -1f table 15. status and control register descriptions
50 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet status and event bits register fedcba9 876number (offset) name interrupt status queue 0 (0120h) isq reserved (register contents undefined) 2 extra data runt crc error broad- cast individ- ual adr hashed rxok dribble bits iahash 4 (0124h) rx event hash table index (alternate rxevent meaning if hashed = 1 and rxok = 1) hashed rxok dribble bits iahash 4 (0124h) rx eventalt reserved (register contents undefined) 6 16coll number-of-tx-collisions jabber out-of- window txok sqe error loss-of- crs 8 (0128h) txevent reserved (register contents undefined) a rx dest rx128 rxmiss txunder- run rdy4tx rxdma frame swint c (012ch) buf event reserved (register contents undefined) e 10-bit receive miss (rxmiss) counter, cleared when read 10 (0130h) rxmiss 10-bit transmit collision (txcol) counter, cleared when read 12 (0132h) txcol crs polarity ok 10bt aui linkok 14 (0134h) linest eesize el present eepro m ok eepro mpresent sibusy initd 3.3 v active 16 (0136h) selfst rdy4tx now txbid err 18 (0138h) busst reserved (register contents undefined) 1a 10-bit aui time domain reflectometer (tdr) counter, cleared when read 1c (013ch) tdr reserved (register contents undefined) 1e table 15. status and control register descriptions (continued)
ds271pp4 51 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.4.5 register 0: interrupt status queue (isq, read-only, address: packetpage base + 0120h) the interrupt status queue register is used in both memory mode and i/o mode to provide the host with interrupt information. whenever an event occurs that triggers an enabled interrupt, the CS8900A sets the appropriate bit(s) in one of five registers, maps the contents of that register to the isq register, and drives an irq pin high. three of the registers mapped to isq are event registers: rxevent (register 4), txevent (register 8), and bufevent (register c). the other two registers are counter-overflow reports: rxmiss (register 10) and txcol (register 12). in mem- ory mode, isq is located at packetpage base + 120h. in i/o mode, isq is located at i/o base + 0008h. see section 5.1 on page 78. regnum the lower six bits describe which register (4, 8, c, 10 or 12) is contained in the isq. regcontent the upper ten bits contain the register data contents. reset value is: 0000 0000 0000 0000 76543210 regcontent regnum fedcba9 8 regcontent
52 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.4.6 register 3: receiver configuration (rxcfg, read/write, address: packetpage base + 0102h) rxcfg determines how frames will be transferred to the host and what frame types will cause interrupts. 000011 these bits provide an internal address used by the CS8900A to identify this as the receiver configuration register. skip_1 when set, this bit causes the last committed received frame to be deleted from the receive buff- er. to skip another frame, the host must rewrite a ? 1 ? to this bit. this bit is not to be used if rxdmaonly (bit 9) is set. skip_1 is an act-once bit. see section 5.2.5 on page 83. streame when set, streamtransfer mode is used to transfer receive frames that are back-to-back and that pass the destination address filter (see section 5.3 on page 86). when streame is clear, streamtransfer mode is not used. this bit must not be set unless either bit autorxdma or bit rxdmaonly is set. rxokie when set, there is an rxok interrupt if a frame is received without errors. rxok interrupt is not generated when dma mode is used for frame reception. rxdmaonly the receive-dma mode is used for all receive frames when this bit is set. autorxdmae when set, the CS8900A will automatically switch to receive-dma mode if the conditions spec- ified in section 5.5 on page 92 are met. rxdmaonly (bit 9) has precedence over autorxd- mae. buffercrc when set, the received crc is included with the data stored in the receive-frame buffer, and the four crc bytes are included in the receive-frame length (packetpage base + 0402h). when clear, neither the receive buffer nor the receive length include the crc. crcerrorie when set, there is a crcerror interrupt if a frame is received with a bad crc. runtie when set, there is a runt interrupt if a frame is received that is shorter than 64 bytes. the CS8900A always discards any frame that is shorter than 8 bytes. extradataie when set, there is an extradata interrupt if a frame is received that is longer than 1518 bytes. the operation of this bit is independent of the received packet integrity (good or bad crc). after reset, if no eeprom is found by the CS8900A, then the register has the following initial state. if an eeprom is found, then the register ? s initial value may be set by the eeprom. see section 3.3 on page 18. reset value is: 0000 0000 0000 0011 76543210 streame skip_1 000011 fedcba9 8 extradataie runtie crcerrorie buffercrc autorx dmae rxdma only rxokie
ds271pp4 53 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.4.7 register 4: receiver event (rxevent, read-only, address: packetpage base + 0124h) alternate meaning if bits 8 and 9 are both set (see section 5.3 on page 86 for exception regarding broadcast frames). rxevent reports the status of the current received frame. 000100 these bits identify this as the receiver event register. when reading this register, these bits will be 000100, where the lsb corresponds to bit 0. iahash if the received frame ? s destination address is accepted by the hash filter, then this bit is set if, and only if iahasha (register 5, rxctl, bit 6) is set, and hashed (bit 9) is set. see section 5.3 on page 86. dribblebits if set, the received frame had from one to seven bits after the last received full byte. an "align- ment error" occurs when dribblebits and crcerror (bit c) are both set. rxok if set, the received frame had a good crc and valid length (i.e., there is not a crc error, runt error, or extradata error). when rxok is set, then the length of the received frame is contained at packetpage base + 0402h. if rxokie (register 3, rxcfg, bit 8) is set, there is an interrupt. hashed if set, the received frame had a destination address that was accepted by the hash filter. if hashed and rxok (bit 8) are set, bits f through a of rxevent become the hash table index for this frame [see section 5.3 on page 86 for an exception regarding broadcast frames!].if hashed and rxok are not both set, then bits f through a are individual event bits as defined below. individualadr if the received frame had a destination address which matched the individual address found at packetpage base + 0158h, then this bit is set if, and only if, rxok (bit 8) is set and individ- uala (register 5, rxctl, bit a) is set. broadcast if the received frame had a broadcast address (ffff ffff ffffh) as the destination ad- dress, then this bit is set if, and only if, rxok is set and broadcasta (register 5, rxctl, bit b) is set. crcerror if set, the received frame had a bad crc. if crcerrorie (register 3, rxcfg, bit c) is set, there is an interrupt runt if set, the received frame was shorter than 64 bytes. if runtie (register 3, rxcfg, bit d) is set, there is an interrupt. extradata if set, the received frame was longer than 1518 bytes. all bytes beyond 1518 are discarded. if extradataie (register 3, rxcfg, bit e) is set, there is an interrupt. reset value is: 0000 0000 0000 0100 notes: 3. all rxevent bits are cleared upon readout. the host is responsible for processing all event bits. 4. rxstatus register (packetpage base + 0400h) is the same as the rxevent register except rxstatus is not cleared when rxevent is read. see section 5.2 on page 78 . the value in the rxevent register is undefined when rxdmaonly bit (bit 9, register 3, rxcfg) is set. 76543210 dribblebits iahash 000100 fedcba9 8 extradata runt crcerror broadcast individual adr hashed rxok 76543210 dribblebits iahash 000100 fedcba9 8 hash table index (see section 5.3 on page 86) hashed = 1 rxok = 1
54 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.4.8 register 5: receiver control (rxctl, read/write, address: packetpage base +0104h) rxctl has two functions: bits 8, c, d, and e define what types of frames to accept. bits 6, 7, 9, a, and b configure the destination address filter. see section 5.3 on page 86. 000101 these bits provide an internal address used by the CS8900A to identify this as the receiver control register. for a received frame to be accepted, the destination address of that frame must pass the filter criteria found in bits 6, 7, 9, a, and b (see section 5.3 on page 86). iahasha when set, receive frames are accepted when the destination address is an individual address that passes the hash filter. promiscuousa frames with any address are accepted when this bit is set. rxoka when set, the CS8900A accepts frames with correct crc and valid length (valid length is: 64 bytes <= length <= 1518 bytes). multicasta when set, receive frames are accepted if the destination address is an multicast address that passes the hash filter. individuala when set, receive frames are accepted if the destination address matches the individual ad- dress found at packetpage base + 0158h to packetpage base + 015dh. broadcasta when set, receive frames are accepted if the destination address is ffff ffff ffffh. crcerrora when set, receive frames that pass the destination address filter, but have a bad crc, are ac- cepted. when clear, frames with bad crc are discarded. see note 5. runta when set, receive frames that are smaller than 64 bytes, and that pass the destination address filter are accepted. when clear, received frames less that 64 bytes in length are discarded. the CS8900A discards any frame that is less than 8 bytes. see note 5. extradataa when set, receive frames longer than 1518 bytes and that pass the destination address filter are accepted. the CS8900A accepts only the first 1518 bytes and ignores the rest. when clear, frames longer than 1518 bytes are discarded. see note 5. after reset, if no eeprom is found by the CS8900A, then the register has the following initial state. if an eeprom is found, then the register ? s initial value may be set by the eeprom. see section 5.3 on page 86. reset value is: 0000 0000 0000 0101 notes: 5. typically, when bits crcerrora, runta and extradataa are cleared (meaning bad frames are being discarded), then the corresponding bits crcerrorie, runtie and extradataie should be set in register 3 (receiver configuration register) to allow the device driver to keep track of discarded frames. 76543210 promiscuousa iahasha 000101 fedcba9 8 extradataa runta crcerrora broadcasta individuala multicasta rxoka
ds271pp4 55 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.4.9 register 7: transmit configuration (txcfg, read/write, address: packetpage base + 0106h) each bit in txcfg is an interrupt enable. when set, the interrupt is enabled as described below. when clear, there is no interrupt. 000111 these bits provide an internal address used by the CS8900A to identify this as the transmit configuration register. loss-of-crsie if the CS8900A starts transmitting on the aui and does not see the carrier sense signal at the end of the preamble, an interrupt is generated if this bit is set. carrier sense activity is reported by the crs bit (register 14, linest, bit e). sqerrorie when set, an interrupt is generated if there is an sqe error. (at the end of a transmission on the aui, the CS8900A expects to see a collision within 64 bit times. if this does not happen, there is an sqe error.) txokie when set, an interrupt is generated if a packet is completely transmitted. out-of-windowie when set, an interrupt is generated if a late collision occurs (a late collision is a collision which occurs after the first 512 bit times). when this occurs, the CS8900A forces a bad crc and ter- minates the transmission. jabberie when set, an interrupt is generated if a transmission is longer than approximately 26 ms. anycollie when set, if one or more collisions occur during the transmission of a packet, an interrupt oc- curs at the end of the transmission 16collie if the CS8900A encounters 16 normal collisions while attempting to transmit a particular packet, the CS8900A stops attempting to transmit that packet. when this bit is set, there is an interrupt upon detecting the 16th collision. after reset, if no eeprom is found by the CS8900A, then the register has the following initial state. if an eeprom is found, then the register ? s initial value may be set by the eeprom. see section 3.3 on page 18. reset value is: 0000 0000 0000 0111 notes: bit 8 (txokie) and bit b (anycollie) are interrupts for normal transmit operation. bits 6, 7, 9, a, and f notes:are interrupts for abnormal transmit operation. 76543210 sqe errorie loss-of-crsie 000111 fedcba9 8 16collie anycollie jabberie out-of-window txokie
56 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.4.10 register 8: transmitter event (txevent, read-only, address: packetpage base + 0128h) txevent gives the event status of the last packet transmitted. 001000 these bits provide an internal address used by the CS8900A to identify this as the transmitter event register. loss-of-crs if the CS8900A is transmitting on the aui and doesn ? t see carrier sense (crs) at the end of the preamble, there is a loss-of-carrier error and this bit is set. if loss-of-crsie (register 7, txcfg, bit 6) is set, there is an interrupt. sqeerror at the end of a transmission on the aui, the CS8900A expects to see a collision within 64 bit times. if this does not happen, there is an sqe error and this bit is set. if sqeerrorie (register 7, txcfg, bit 7) is set, there is an interrupt. txok this bit is set if the last packet was completely transmitted (jabber (bit a), out-of-window-colli- sion (bit 9), and 16coll (bit f) must all be clear). if txokie (register 7, txcfg, bit 8) is set, there is an interrupt. out-of-window this bit is set if a collision occurs more than 512 bit times after the first bit of the preamble. when this occurs, the CS8900A forces a bad crc and terminates the transmission. if out-of-window- ie (register 7, txcfg, bit 9) is set, there is an interrupt jabber if the last transmission is longer than 26 msec, then the packet output is terminated by the jab- ber logic and this bit is set. if jabberie (register 7, txcfg, bit a) is set, there is an interrupt. #-of-tx-collisions these bits give the number of transmit collisions that occurred on the last transmitted packet. bit b is the lsb. if anycollie (register 7, txcfg, bit b) is set, there is an interrupt when any collision occurs. 16coll this bit is set if the CS8900A encounters 16 normal collisions while attempting to transmit a particular packet. when this happens, the CS8900A stops further attempts to send that packet. if 16collie (register 7, txcfg, bit f) is set, there is an interrupt. reset value is: 0000 0000 0000 1000 notes: 1.in any event register, like txevent, all bits are cleared upon readout. the host is responsible for processing all event bits. 2.txok (bit 8) and the number-of-tx-collisions (bits e-b) are used in normal packet transmission.all other bits (6, 7, 9, a, and f) give the status of abnormal transmit operation. 76543210 sqeerror loss-of-crs 001000 fedcba9 8 16coll number-of-tx-collisions jabber out-of-window txok
ds271pp4 57 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.4.11 register 9: transmit command status (txcmd, read-only, address: packetpage base + 0108h) this register contains the latest transmit command which tells the CS8900A how the next packet should be sent. the command must be written to packetpage base + 0144h in order to initiate a transmission. the host can read the command from register 9 (packetpage base + 0108h). see section 5.7 on page 98. 001001 these bits provide an internal address used by the CS8900A to identify this as the transmit command register. when reading this register, these bits will be 001001, where the lsb cor- responds to bit 0. txstart this pair of bits determines how many bytes are transferred to the CS8900A before the mac starts the packet transmit process. bit 7 bit 6 0 0 start transmission after 5 bytes are in the CS8900A 0 1 start transmission after 381 bytes are in the CS8900A 1 0 start transmission after 1021 bytes are in the CS8900A 1 1 start transmission after the entire frame is in the CS8900A force when set in conjunction with a new transmit command, any transmit frames waiting in the trans- mit buffer are deleted. if a previous packet has started transmission, that packet is terminated within 64 bit times with a bad crc. onecoll when this bit is set, any transmission will be terminated after only one collision. when clear, the CS8900A allows up to 16 normal collisions before terminating the transmission. inhibitcrc when set, the crc is not appended to the transmission. txpaddis when txpaddis is clear, if the host gives a transmit length less than 60 bytes and inhibitcrc is set, then the CS8900A pads to 60 bytes. if the host gives a transmit length less than 60 bytes and inhibitcrc is clear, then the CS8900A pads to 60 bytes and appends the crc. when txpaddis is set, the CS8900A allows the transmission of runt frames (a frame less than 64 bytes). if inhibitcrc is clear, the CS8900A appends the crc. if inhibitcrc is set, the CS8900A does not append the crc after reset, if no eeprom is found by the CS8900A, then the register has the following initial state. if an eeprom is found, then the register ? s initial value may be set by the eeprom. see section 3.3 on page 18. register value is: 0000 0000 0000 1001 notes: the CS8900A does not transmit a frame if txlength < 3 76543210 txstart 001001 fedcba9 8 txpaddis inhibitcrc onecoll force
58 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.4.12 register b: buffer configuration (bufcfg, read/write, address: packetpage base + 010ah) each bit in bufcfg is an interrupt enable. when set, the interrupt described below is enabled. when clear, there is no interrupt. 001011 these bits provide an internal address used by the CS8900A to identify this as the buffer con- figuration register. swint-x when set, there is an interrupt requested by the host software. the CS8900A provides the in- terrupt, and sets the swint (register c, bufevent, bit 6) bit. the CS8900A acts upon this com- mand at once. swint-x is an act-once bit. to generate another interrupt, rewrite a "1" to this bit. rxdmaie when set, there is an interrupt when a frame has been received and dma is complete. with this interrupt, the rxdmaframe bit (register c, bufevent, bit 7) is set. rdy4txie when set, there is an interrupt when the CS8900A is ready to accept a frame from the host for transmission. (see section 5.7 on page 98 for a description of the transmit bid process.) txunderrunie when set, there is an interrupt if the CS8900A runs out of data before it reaches the end of the frame (called a transmit underrun). when this happens, event bit txunderrun (register c, bufevent, bit 9) is set and the CS8900A makes no further attempts to transmit that frame. if the host still wants to transmit that particular frame, the host must go through the transmit request process again. rxmissie when set, there is an interrupt if one or more received frames is lost due to slow movement of receive data out of the receive buffer (called a receive miss). when this happens, the rxmiss bit (register c, bufevent, bit a) is set. rx128ie when set, there is an interrupt after the first 128 bytes of a frame have been received. this al- lows a host processor to examine the destination address, source address, length, sequence number, and other information before the entire frame is received. this interrupt should not be used with dma. thus, if either autorxdma (register 3, rxcfg, bit a) or rxdmaonly (register 3, rxcfg, bit 9) is set, the rx128ie bit must be clear. txcolovfie if set, there is an interrupt when the txcol counter increments from 1ffh to 200h. (the txcol counter (register 18) is incremented whenever the CS8900A sees that the rxd+/rxd- pins (10base-t) or the ci+/ci- pins (aui) go active while a packet is being transmitted.) missovfloie if missovfloie is set, there is an interrupt when the rxmiss counter increments from 1ffh to 200h. (a receive miss is said to have occurred if packets are lost due to slow movement of re- ceive data out of the receive buffers. when this happens, the rxmiss bit (register c, bufevent, bit a) is set, and the rxmiss counter (register 10) is incremented.) rxdestie when set, there is an interrupt when a receive frame passes the destination address filter cri- teria defined in the rxctl register (register 5). this bit provides an early indication of an in- coming frame. it is earlier than rx128 (register c, bufevent, bit b). if rxdestie is set, the bufevent could be rxdest or rx128. after 128 bytes are received, the bufevent changes from rxdest to rx128. after reset, if no eeprom is found by the CS8900A, then the register has the following initial state after reset. if an eeprom is found, then the register ? s initial value may be set by the eeprom. see section 3.3 on page 18. reset value is: 0000 0000 0000 1011 76543210 rxdmaie swint-x 001011 fedcba9 8 rxdestie miss ovfloie txcol ovfloie rx128ie rxmissie txunder runtie rdy4txie
ds271pp4 59 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.4.13 register c: buffer event (bufevent, read-only, address: packetpage base + 012ch) bufevent gives the status of the transmit and receive buffers. 001100 these bits provide an internal address used by the CS8900A to identify this as the buffer event register. when reading this register, these bits will be 001100, where the lsb corresponds to bit 0. swint if set, there has been a software initiated interrupt. this bit is used in conjunction with the swint- x bit (register b, bufcfg, bit 6). rxdmaframe if set, one or more received frames have been transferred by slave dma. if rxdmaie (register b, bufcfg, bit 7) is set, there is an interrupt. rdy4tx if set, the CS8900A is ready to accept a frame from the host for transmission. if rdy4txie (reg- ister b, bufcfg, bit 8) is set, there is an interrupt. (see section 5.7 on page 98 for a description of the transmit bid process.) txunderrun this bit is set if CS8900A runs out of data before it reaches the end of the frame (called a trans- mit underrun). if txunderrunie (register b, bufcfg, bit 9) is set, there is an interrupt. rxmiss if set, one or more receive frames have been lost due to slow movement of data out of the re- ceive buffers. if rxmissie (register b, bufcfg, bit a) is set, there is an interrupt. rx128 this bit is set after the first 128 bytes of an incoming frame have been received. this bit will allow the host the option of preprocessing frame data before the entire frame is received. if rx128ie (register b, bufcfg, bit b) is set, there is an interrupt. rxdest when set, this bit shows that a receive frame has passed the destination address filter criteria as defined in the rxctl register (register 5). this bit is useful as an early indication of an in- coming frame. it will be earlier than rx128 (register c, bufevent, bit b). if rxdestie (register b, bufcfg, bit f) is set, there is an interrupt. reset value is: 0000 0000 0000 1100 notes: with any event register, like bufevent, all bits are cleared upon readout. the host is responsible for processing all event bits. 76543210 rxdma frame swint 001100 fedcba9 8 rxdest rx128 rxmiss txunder run rdy4tx
60 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.4.14 register 10: receiver miss counter (rxmiss, read-only, address: packetpage base + 0130h) the rxmiss counter (bits 6 through f) records the number of receive frames that are lost (missed) due to the lack of available buffer space. if the missovfloie bit (register b, bufcfg, bit d) is set, there is an interrupt when rxmiss increments from 1ffh to 200h. this interrupt provides the host with an early warning that the rxmiss counter should be read before it reaches 3ffh and starts over (by interrupting at 200h, the host has an additional 512 counts before rxmiss actually overflows). the rxmiss counter is cleared when read. 010000 these bits provide an internal address used by the CS8900A to identify this as the receiver miss counter. when reading this register, these bits will be 010000, where the lsb corre- sponds to bit 0. misscount the upper ten bits contain the number of missed frames. register ? s value is: 0000 0000 0001 0000 76543210 misscount 010000 fedcba9 8 misscount
ds271pp4 61 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.4.15 register 10: transmit collision counter (txcol, read-only, address: packetpage base + 0132h) the txcol counter (bits 6 through f) is incremented whenever the 10base-t receive pair (rxd+ / rxd-) or aui collision pair (ci+ / ci-) becomes active while a packet is being transmitted. if the txcolovfie bit (register b, bufcfg, bit c) is set, there is an interrupt when txcol increments from 1ffh to 200h. this interrupt provides the host with an early warning that the txcol counter should be read before it reaches 3ffh and starts over (by inter- rupting at 200h, the host has an additional 512 counts before txcol actually overflows). the txcol counter is cleared when read. 010010 these bits provide an internal address used by the CS8900A to identify this as the transmit collision counter. when reading this register, these bits will be 010010, where the lsb corre- sponds to bit 0. colcount the upper ten bits contain the number of collisions. reset value is: 0000 0000 0001 0010 76543210 colcount 010010 fedcba9 8 colcount
62 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.4.16 register 13: line control (linectl, read/write, address: packetpage base + 0112h) linectl determines the configuration of the mac engine and physical interface. 010011 these bits provide an internal address used by the CS8900A to identify this as the line control register. serrxon when set, the receiver is enabled. when clear, no incoming packets pass through the receiver. if serrxon is cleared while a packet is being received, reception is completed and no subse- quent receive packets are allowed until serrxon is set again. sertxon when set, the transmitter is enabled. when clear, no transmissions are allowed. if sertxon is cleared while a packet is being transmitted, transmission is completed and no subsequent packets are transmitted until sertxon is set again. auionly bits 8 and 9 are used to select either the aui or the 10base-t interface according to the fol- lowing: [note: 10base-t transmitter will be inactive even when selected unless link pulses are detected or bit disablelt (register 19) is set. auionly (bit 8) autoaui/10bt (bit 9) physical interface 1 n/a aui 0> 0 10base-t 0 1 auto-select autoaui/10bt see auionly (bit 8) description above. modbackoffe when clear, the iso/iec standard backoff algorithm is used (see section 3.9 on page 27). when set, the modified backoff algorithm is used. (the modified backoff algorithm extends the backoff delay after each of the first three tx collisions.) polaritydis the 10base-t receiver automatically determines the polarity of the received signal at the rxd+/rxd- input (see section 3.11 on page 34). when this bit is clear, the polarity is correct- ed, if necessary. when set, no effort is made to correct the polarity. this bit is independent of the polarityok bit (register 14, linest, bit c), which reports whether the polarity is normal or reversed. 2-partdefdis before a transmission can begin, the CS8900A follows a deferral procedure. with the 2-part- defdis bit clear, the CS8900A uses the standard two-part deferral as defined in iso/iec 8802- 3 paragraph 4.2.3.2.1. with the 2-partdefdis bit set, the two-part deferral is disabled. lorxsquelch when clear, the 10base-t receiver squelch thresholds are set to levels defined by the iso/iec 8802-3 specification. when set, the thresholds are reduced by approximately 6db. this is use- ful for operating with "quiet" cables that are longer than 100 meters. after reset, if no eeprom is found by the CS8900A, then the register has the following initial state. if an eeprom is found, then the register ? s initial value may be set by the eeprom. see section 3.3 on page 18. reset value is: 0000 0000 0001 0011 76543210 sertxon serrxon 010011 fedcba9 8 lorx squelch 2-part defdis polaritydis mod backoffe auto aui/10bt auionly
ds271pp4 63 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.4.17 register 14: line status (linest, read-only, address: packetpage base + 0134h) linest reports the status of the ethernet physical interface. 010100 these bits provide an internal address used by the CS8900A to identify this as the line status register. when reading this register, these bits will be 010100, where the lsb corresponds to bit 0. linkok if set, the 10base-t link has not failed. when clear, the link has failed, either because the CS8900A has just come out of reset, or because the receiver has not detected any activity (link pulses or received packets) for at least 50 ms. aui if set, the CS8900A is using the aui. 10bt if set, the CS8900A is using the 10base-t interface. polarityok if set, the polarity of the 10base-t receive signal (at the rxd+ / rxd- inputs) is correct. if clear, the polarity is reversed. if polaritydis (register 13, linectl, bit c) is clear, the polarity is auto- matically corrected, if needed. the polarityok status bit shows the true state of the incoming polarity independent of the polaritydis control bit. thus, if polaritydis is clear and polarityok is clear, then the receive polarity is inverted, and corrected. crs this bit tells the host the status of an incoming frame. if crs is set, a frame is currently being received. crs remains asserted until the end of frame (eof). at eof, crs goes inactive in about 1.3 to 2.3 bit times after the last low-to-high transition of the recovered data. reset value is: 0000 0000 0001 0100 76543210 linkok 010100 fedcba9 8 crs polarityok 10bt aui
64 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.4.18 register 15: self control (selfctl, read/write, address: packetpage base + 0114h) selfctl controls the operation of the led outputs and the lower-power modes. 010101 these bits provide an internal address used by the CS8900A to identify this as the chip self control register. reset when set, a chip-wide reset is initiated immediately. reset is an act-once bit. this bit is cleared as a result of the reset. swsuspend when set, the CS8900A enters the software initiated suspend mode. upon entering this mode, there is a partial reset. all registers and circuits are reset except for the isa i/o base address register and the selfctl register. there is no transmit nor receive activity in this mode. to come out of software suspend, the host issues an i/o write within the CS8900A ? s assigned i/o space (see section 3.7 on page 25 for a complete description of the CS8900A ? s low-power modes). hwsleepe when set, the sleep input pin is enabled. if sleep is high, the CS8900A is "awake", or oper- ative (unless in swsuspend mode, as shown above). if sleep is low, the CS8900A enters ei- ther the hardware standby or hardware suspend mode. when clear, the CS8900A ignores the sleep input pin (see section 3.7 on page 25 for a complete description of the CS8900A ? s low- power modes). hwstandbye if hwsleepe is set and the sleep input pin is low, then when hwstandbye is set, the CS8900A enters the hardware standby mode. when clear, the CS8900A enters the hardware suspend mode (see section 3.7 on page 25 for a complete description of the CS8900A ? s low- power modes). hc0e the linkled or hc0 output pin is selected with this control bit. when hc0e is clear, the output pin is linkled . when hc0e is set, the output pin is hc0 and the hcb0 bit (bit e) controls the pin. hc1e the bstatus or hc1 output pin is selected with this control bit. when hc1e is clear, the out- put pin is bstatus and indicates receiver isa bus activity. when hc1e is set, the output pin is hc1 and the hcb1 bit (bit f) controls the pin. hcb0 when hc0e (bit c) is set, this bit controls the hc0 pin. if hcb0 is set, hc0 is low. if hcb0 is clear, hc0 is high. hc0 may drive an led or a logic gate. when hc0e (bit c) is clear, this con- trol bit is ignored. hcb1 when hc1e (bit d) is set, this bit controls the hc1 pin. if hcb1 is set, hc1 is low. if hcb1 is clear, hc1 is high. hc1 may drive an led or a logic gate. when hc1e (bit d) is clear, this con- trol bit is ignored. after reset, if no eeprom is found by the CS8900A, then the register has the following initial state. if an eeprom is found, then the register ? s initial value may be set by the eeprom. see section 3.3 on page 18. reset value is: 0000 0000 0001 0101 76543210 reset 010101 fedcba9 8 hcb1 hcb0 hc1e hc0e hw standby hwsleepe sw suspend
ds271pp4 65 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.4.19 register 16: self status (selfst, read-only, address: packetpage base + 0136h) selfst reports the status of the eeprom interface and the initialization process. 010110 these bits provide an internal address used by the CS8900A to identify this as the chip self status register. when reading this register, these bits will be 010110, where the lsb corre- sponds to bit 0. 3,3vactive if the CS8900A is operating on a 3.3v supply, this bit is set. if the CS8900A is operating on a 5v supply, this bit is clear. initd if set, the CS8900A initialization, including read-in of the eeprom, is complete. sibusy if set, the eecs output pin is high indicating that the eeprom is currently being read or pro- grammed. the host must not write to packetpage base + 0040h nor 0042h until sibusy is clear. eeprompresent if the eedatain pin is low after reset, there is no eeprom present, and the eeprompresent bit is clear. if the eedatain pin is high after reset, the CS8900A "assumes" that an eeprom is present, and this bit is set. eepromok if set, the checksum of the eeprom readout was ok. elpresent if set, external logic for latchable address bus decode is present. eesize this bit shows the size of the attached eeprom and is valid only if the eeprompresent bit (bit 9) and eepromok bit (bit a) are both set. if clear, the eeprom size is either 128 words ( ? c56 or ? cs56) or 256 words (c66 or ? cs66). if set, the eeprom size is 64 words ( ? c46 or ? cs46). reset value is: 0000 0000 0001 0110 76543210 initd 3.3v active 010110 fedcba9 8 eesize elpresent eeprom ok eeprom present sibusy
66 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.4.20 register 17: bus control (busctl, read/write, address: packetpage base + 0116h) busctl controls the operation of the isa-bus interface. 010111 these bits provide an internal address used by the CS8900A to identify this as the bus control register. resetrxdma when set, the rxdma offset pointer at packetpage base + 0026h is reset to zero. when the host sets this bit, the CS8900A does the following: 1.terminates the current receive dma activity, if any. 2.clears all internal receive buffers. 3.zeroes the rxdma offset pointer. dmaextend when set, dmarqx goes inactive on the falling edge of ior n instead of the rising edge of ior n -1 . see switching characteristics, dma read, t dmar5 . setting this bit also enables single transfer mode dma. normal operation is demand mode dma in which dmackx cannot deas- sert until after dmarqx deasserts, i.e. until a full ethernet frame is transferred. single transfer mode allows dmackx to deassert between each dma read. usesa when set, the memcs16 pin goes low whenever the address on sa bus [12..19] match the CS8900A ? s assigned memory base address and the chipsel pin is low (internal address de- code). when clear, memcs16 is driven low whenever chipsel goes low. (external address decode). see section 4.9 on page 73. for memcs16 pin to be enabled, the CS8900A must be in memory mode with the memorye bit (register 17, busctl, bit a) set. memorye when set, the CS8900A may operate in memory mode. when clear, memory mode is disabled. i/o mode is always enabled. dmaburst when clear, the CS8900A performs continuous dma until the receive frame is completely transferred from the CS8900A to host memory. when set, each dma access is limited to 28us, after which time the CS8900A gives up the bus for 1.3us before making a new dma request. iochrdye when set, the CS8900A does not use the iochrdy output pin, and the pin is always high-im- pedance. this allows external pull-up to force the output high. when clear, the CS8900A drives iochrdy low to request additional time during i/o read and memory read cycles. iochrdy does not affect i/o write, memory write, nor dma read. rxdmasize this bit determines the size of the receive dma buffer (located in host memory). when set, the dma buffer size is 64 kbytes. when clear, it is 16 kbytes. enablerq when set, the CS8900A will generate an interrupt in response to an interrupt event (section 5.1). when cleared, the CS8900A will not generate any interrupts. after reset, if no eeprom is found by the CS8900A, then the register has the following initial state. if an eeprom is found, then the register ? s initial value may be set by the eeprom. see section 3.3 on page 18. reset value is: 0000 0000 0001 0111 76543210 reset rxdma 010111 fedcba9 8 enableirq rxdma size ioch rdye dmaburst memorye usesa dmaextend
ds271pp4 67 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.4.21 register 18: bus status (busst, read-only, address: packetpage base + 0138h) busst describes the status of the current transmit operation. 011000 these bits provide an internal address used by the CS8900A to identify this as the bus status register. when reading this register, these bits will be 011000, where the lsb corresponds to bit 0. txbiderr if set, the host has commanded the CS8900A to transmit a frame that the CS8900A will not send. frames that the CS8900A will not send are: 1) any frame greater than 1514 bytes, provided that inhibitcrc (register 9, txcmd, bit c) is clear. 2) any frame greater than 1518 bytes. note that this bit is not set when transmit frames are too short. rdy4txnow rdy4txnow signals the host that the CS8900A is ready to accept a frame from the host for transmission. this bit is similar to rdy4tx (register c, bufevent, bit 8) except that there is no interrupt associated with rdy4txnow. the host can poll the CS8900A and check rdy4txnow to determine if the CS8900A is ready for transmit. (see section 5.7 on page 98 for a description of the transmit bid process.) reset value is: 0000 0000 0001 1000 76543210 txbiderr 011000 fedcba9 8 rdy4tx now
68 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.4.22 register 19: test control (testctl, read/write, address: packetpage base + 0118h) testctl controls the diagnostic test modes of the CS8900A. 011001 these bits provide an internal address used by the CS8900A to identify this as the test control register. disablelt when set, the 10base-t interface allows packet transmission and reception regardless of the link status. disablelt is used in conjunction with the linkok (register 14, linest, bit 7) as fol- lows: linkok disablelt 0 0 no packet transmission for reception allowed. transmitter sends link impulses. 0 1 disablelt overrides linkok to allow packet transmission and reception. transmitter does not send link pulses. 1 n/a disable has no meaning if linkok = 1. endecloop when set, the CS8900A enters internal loopback mode where the internal manchester encoder output is connected to the decoder input. the 10base-t and aui transmitters and receivers are disabled. when clear, the CS8900A is configured for normal operation. auiloop when set, the CS8900A allows reception while transmitting. this facilitates loopback tests for the aui. when clear, the CS8900A is configured for normal aui operation. disable backoff when set, the backoff algorithm is disabled. the CS8900A transmitter looks only for completion of the inter packet gap before starting transmission. when clear, the backoff algorithm is used. fdx when set, 10base-t full duplex mode is enabled and crs (register 14, linest, bit e) is ig- nored. this bit must be set when performing loopback tests on the 10base-t port. when clear, the CS8900A is configured for standard half-duplex 10base-t operation. at reset, if no eeprom is found by the CS8900A, then the register has the following initial state. if an eeprom is found, then the register ? s initial value may be set by the eeprom. see section 3.3 on page 18. reset value is: 0000 0000 0001 1001 76543210 disablelt 011001 fedcba9 8 fdx disable back- off auiloop endec loop
ds271pp4 69 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.4.23 register 1c: aui time domain reflectometer (read-only, address: packetpage base + 013ch) the tdr counter (bits 6 through f) is a time domain reflectometer useful in locating cable faults in 10base-2 and 10base-5 coax networks. it counts at a 10 mhz rate from the beginning of transmission on the aui to when a col- lision or loss-of-carrier error occurs. the tdr counter is cleared when read. 011100 these bits provide an internal address used by the CS8900A to identify this as the bus status register. when reading this register, these bits will be 011100, where the lsb corresponds to bit 0. aui-delay the upper ten bits contains the number of 10 mhz clock periods between the beginning of transmission on the aui to when a collision or loss-of-carrier error occurs. reset value is: 0000 0000 0001 1100 76543210 aui delay 011100 fedcba9 8 aui delay
70 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.5 initiate transmit registers 4.5.1 transmit command request - txcmd (write-only, address: packetpage base + 0144h) the word written to packetpage base + 0144h tells the CS8900A how the next packet should be transmitted. this packetpage location is write-only, and the written word can be read from register 9, at packetpage base + 0108h. the CS8900A does not transmit a frame if txlength (at packetpage location base + 0146h) is less than 3. see section 5.7 on page 98. 001001 these bits provide an internal address used by the CS8900A to identify this as the transmit command register. when reading this register, these bits will be 001001, where the lsb cor- responds to bit 0. txstart this pair of bits determines how many bytes are transferred to the CS8900A before the mac starts the packet transmit process. bit 7 bit 6 0 0 start transmission after 5 bytes are in the CS8900A 0 1 start transmission after 381 bytes are in the CS8900A 1 0 start transmission after 1021 bytes are in the CS8900A 1 1 start transmission after the entire frame is in the CS8900A force when set in conjunction with a new transmit command, any transmit frames waiting in the trans- mit buffer are deleted. if a previous packet has started transmission, that packet is terminated within 64 bit times with a bad crc. onecoll when this bit is set, any transmission will be terminated after only one collision. when clear, the CS8900A allows up to 16 normal collisions before terminating the transmission. inhibitcrc when set, the crc is not appended to the transmission. txpaddis when txpaddis is clear, if the host gives a transmit length less than 60 bytes and inhibitcrc is set, then the CS8900A pads to 60 bytes. if the host gives a transmit length less than 60 bytes and inhibitcrc is clear, then the CS8900A pads to 60 bytes and appends the crc. when txpaddis is set, the CS8900A allows the transmission of runt frames (a frame less than 64 bytes). if inhibitcrc is clear, the CS8900A appends the crc. if inhibitcrc is set, the CS8900A does not append the crc. since this register is write-only, it ? s initial state after reset is undefined. 4.5.2 transmit length (write-only, address: packetpage base + 0146h) this register is used in conjunction with register 9, txcmd. when a transmission is initiated via a command in tx- cmd, the length of the transmitted frame is written into this register. the length of the transmitted frame may be modified by the configuration of the txpaddis and inhibitcrc bits in the txcmd register. see table 35, and section 5.7 on page 98. txlength must be >3 and < 1519. since this register is write-only, it ? s initial state after reset is undefined. 76543210 txstart 001001 fedcba9 8 txpaddis inhibitcrc onecoll force address 0147h address 0146h most-significant byte of transmit frame length least-significant byte of transmit frame length
ds271pp4 71 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.6 address filter registers 4.6.1 logical address filter (hash table) (read/write, address: packetpage base + 0150h) the CS8900A hashing decoder circuitry compares its output with one bit of the logical address filter register. if the decoder output and the logical address filter bit match, the frame passes the hash filter and the hashed bit (register 4, rxevent, bit 9) is set. see section 5.3 on page 86. reset value is: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4.6.2 individual address (ieee address) (read/write, address: packetpage base + 0158h) the unique, ieee 48-bit individual address (ia) begins at 0158h. the first bit of the ia (bit ia[00]) must be "0". see section 5.3 on page 86. the value of this register must be loaded from external storage, for example, from the eeprom. see section 3.3 on page 18. if the CS8900A is not able to load the ia from the eeprom, then after a reset this register is undefined, and the driver must write an address to this register. address 0157h address 0156h address 0155h address 0154h address 0153h address 0152h address 0151h address 0150h most-signifi- cant byte of hash filter. least-signifi- cant byte of hash filter. address 0015dh address 0015ch address 0015bh address 0015ah address 0159h address 00158h octet 5 of ia octet 0 of ia
72 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 4.7 receive and transmit frame locations the receive and transmit frame packetpage loca- tions are used to transfer ethernet frames to and from the host. the host sequentially writes to and reads from these locations, and internal buffer memory is dynamically allocated between transmit and receive as needed. one receive frame and one transmit frame are accessible at a time. 4.7.1 receive packetpage locations in io mode, the receive status/length/frame loca- tions are read through repetitive reads from one io port at the io base address. see section 4.10 on page 75. in memory mode, the receive status/length/frame locations are read using memory reads of a block of memory starting at memory base address + 0400h. typically the memory locations are read sequen- tially using repetitive move instructions (rep movs). see section 4.9 on page 73. random access is not needed. however, the first 118 bytes of the receive frame can be accessed ran- domly if word reads, on even word boundaries, are used. beyond 118 bytes, the memory reads must be sequential. byte reads, or reads on odd-word boundaries, can be performed only in sequential read mode. see section 4.8 on page 72. the rxstatus word reports the status of the current received frame. rxevent register 4 (packetpage base + 0124h) has the same contents as the rxsta- tus register, except rxevent is cleared when rx- event is read. the rxlength (receive length) word is the length, in bytes, of the data to be transferred to the host across the isa bus. the register describes the length from the start of destination address to the end of crc, assuming that crc has been selected (via register 3 rxcfg, bit buffercrc). if crc has not been selected, then the length does not in- clude the crc, and the crc is not present in the receive buffer. after the rxlength has been read, the receive frame can be read. when some portion of the frame is read, the entire frame should be read before read- ing the rxevent register either directly or through the isq register. reading the rxevent register sig- nals to the CS8900A that the host is finished with the current frame, and wants to start processing the next frame. in this case, the current frame will no longer be accessible to the host. the current frame will also become inaccessible if a skip command is issued, or if the entire frame has been read. see section 5.2 on page 78. 4.7.2 transmit locations the host can write frames into the CS8900A buffer using memory writes using rep movs to the tx- frame location. see section 5.7 on page 98. 4.8 eight and sixteen bit transfers a data transfer to or from the CS8900A can be done in either i/o or memory space, and can be ei- ther 16 bits wide (word transfers) or 8 bits wide (byte transfers). because the CS8900A ? s internal architecture is based on a 16-bit data bus, word transfers are the most efficient. to transfer transmit frames to the CS8900A and re- ceive frames from the CS8900A, the host may mix word and byte transfers, provided it follows three rules: 1) the primary method used to access CS8900A memory is word access. 2) word accesses to the CS8900A ? s internal memory are kept on even-byte boundaries. 3) when switching from byte accesses to word ac- cesses, a byte access to an even byte address must be followed by a byte access to an odd- byte address before the host may execute a word access (this will realign the word transfers to even-byte boundaries). on the other hand, a byte access to an odd-byte address may be fol- lowed by a word access.
ds271pp4 73 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet failure to observe these three rules may cause data corruption. 4.8.1 transferring odd-byte-aligned data some applications gather transmit data from more than one section of host memory. the boundary be- tween the various memory locations may be either even- or odd-byte aligned. when such a boundary is odd-byte aligned, the host should transfer the last byte of the first block to an even address, followed by the first byte of the second block to the follow- ing odd address. it can then resume word transfers. an example of this is shown in figure 17. 4.8.2 random access to CS8900A memory the first 118 bytes of a receive frame held in the CS8900A ? s on-chip memory may be randomly ac- cessed in memory mode. after the first 118 bytes, only sequential access of received data is allowed. either byte or word access is permitted, as long as all word accesses are executed to even-byte bound- aries. 4.9 memory mode operation to configure the CS8900A for memory mode, the packetpage memory must be mapped into a contig- uous 4-kbyte block of host memory. the block must start at an x000h boundary, with the pack- etpage base address mapped to x000h. when the CS8900A comes out of reset, its default configura- tion is i/o mode. once memory mode is selected, all of the CS8900A ? s registers can be accessed di- rectly. in memory mode, the CS8900A supports standard or ready bus cycles without introducing additional wait states. memory moves can use movd (double-word transfers) as long as the CS8900A ? s memory base address is on a double word boundary. since 286 processors don ? t support the movd instruction, word and byte transfers must be used with a 286. 4.9.1 accesses in memory mode the CS8900A allows read/write access to the in- ternal packetpage memory, and read access of the optional boot prom. (see section 3.7 on page 25 for a description of the optional boot prom.) a memory access occurs when all of the following are true: the address on the isa system address bus (sa0 - sa19) is within the memory space range of the CS8900A or boot prom. the chipsel input pin is low. either the memr pin or the memw pin is low. 4.9.2 configuring the CS8900A for memory mode there are two different methods of configuring the CS8900A for memory mode operation. one meth- od allows the CS8900A's internal memory to be mapped anywhere within the host system's 24-bit word transfer word transfer byte transfer word transfer word transfer byte transfer word transfer word transfer first block of data second block of dat a figure 17. odd-byte aligned data description mnemonic read/write location: pocketpage base + receive status rxstatus read-only 0400h-0401h receive length rxlength read-only 0402h-0403h receive frame rxframe read-only starts at 0404h transmit frame txframe write-only starts at 0a00h table 16. receive/transmit memory locations
74 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet memory space. the other method limits memory mapping to the first 1 mbyte of host memory space. general memory mode operation: configuring the CS8900A so that its internal memory can be mapped anywhere within host memory space re- quires the following: a simple circuit must be added to decode the latchable address bus (la20 - la23) and the bale signal. the host must configure the external logic with the correct address range as follows: 1) check to see if the initd bit (register 16, selfst, bit 7) is set, indicating that initial- ization is complete. 2) check to see if the elpresent bit (register 16, selfst, bit b) is set. this bit indicates that external logic for the la bus decode is present. 3) set the elsel bit of the eeprom com- mand register to activate the elcs pin for use with the external decode circuit. 4) configure the external logic serially. the host must write the memory base address into the memory base address register (pack- etpage base + 002ch); the host must set the memorye bit (register 17, busctl, bit a); and the host must set the usesa bit (register 17, busctl, bit 9). limiting memory mode to the first 1 mbyte of host memory space: configuring the CS8900A so that its internal memory can be mapped only within the first 1 mbyte of host memory space requires the following: the chipsel pin must be tied low; the isa-bus smemr signal must be connected to the memr pin; the isa-bus smemw signal must be connect- ed to the memw pin; the host must write the memory base address into the memory base address register (pack- etpage base + 002ch); the host must set the memorye bit (register 17, busctl, bit a); and the host must clear the usesa bit (register 17, busctl, bit 9). 4.9.3 basic memory mode transmit memory mode transmit operations occur in the fol- lowing order (using interrupts): 1) the host bids for storage of the frame by writ- ing the transmit command to the txcmd reg- ister (memory base + 0144h) and the transmit frame length to the txlength register (memory base + 0146h). if the transmit length is errone- ous, the command is discarded and the tx- biderr bit (register 18, busst, bit 7) is set. 2) the host reads the busst register (register 18, memory base + 0138h). if the rdy4txnow bit (bit 8) is set, the frame can be written. if clear, the host must wait for CS8900A buffer memory to become available. if rdy4txie (register b, bufcfg, bit 8) is set, the host will be interrupt- ed when rdy4tx (register c, bufevent, bit 8) becomes set. 3) once the CS8900A is ready to accept the frame, the host executes repetitive memory-to- memory move instructions (rep movs) to memory base + 0a00h to transfer the entire frame from host memory to CS8900A memory. for a more detailed description of transmit, see section 5.7 on page 98. 4.9.4 basic memory mode receive memory mode receive operations occur in the fol- lowing order (interrupts used to signal the presence of a valid receive frame):
ds271pp4 75 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 1) a frame is received by the CS8900A, triggering an enabled interrupt. 2) the host reads the interrupt status queue (memory base + 0120h) and is informed of the receive frame. 3) the host reads rxstatus (memory base + 0400h) to learn the status of the receive frame. 4) the host reads rxlength (memory base + 0402h) to learn the frame ? s length. 5) the host reads the frame data by executing re- petitive memory-to-memory move instructions (rep movs) from memory base + 0404h to transfer the entire frame from CS8900A mem- ory to host memory. for a more detailed description of receive, see section 5.2 on page 78. 4.9.5 polling the CS8900A in memory mode if interrupts are not used, the host can poll the CS8900A to check if receive frames are present and if memory space is available for transmit. however, this is beyond the scope of this data sheet. 4.10 i/o space operation in i/o mode, packetpage memory is accessed through eight 16-bit i/o ports that are mapped into 16 contiguous i/o locations in the host system ? s i/o space. i/o mode is the default configuration for the CS8900A and is always enabled. on power up, the default value of the i/o base address is set at 300h. (note that 300h is typically assigned to lan pe- ripherals). the i/o base address may be changed to any available xxx0h location, either by loading configuration data from the eeprom, or during system setup. table 17 shows the CS8900A i/o mode mapping. 4.10.1 receive/transmit data ports 0 and 1 these two ports are used when transferring trans- mit data to the CS8900A and receive data from the CS8900A. port 0 is used for 16-bit operations and ports 0 and 1 are used for 32-bit operations (lower- order word in port 0). 4.10.2 txcmd port the host writes the transmit command (txcmd) to this port at the start of each transmit operation. the transmit command tells the CS8900A that the host has a frame to be transmitted, as well as how that frame should be transmitted. this port is mapped into packetpage base + 0144h. see regis- ter 9 in section 4.4 on page 46 for more informa- tion. 4.10.3 txlength port the length of the frame to be transmitted is written here immediately after the transmit command is written. this port is mapped into packetpage base + 0146h. 4.10.4 interrupt status queue port this port contains the current value of the interrupt status queue (isq). the isq is located at pack- etpage base + 0120h. for a more detailed descrip- tion of the isq, see section 5.1 on page 78. 4.10.5 packetpage pointer port the packetpage pointer port is written whenever the host wishes to access any of the CS8900A ? s in- ternal registers. the first 12 bits (bits 0 through b) provide the internal address of the target register to be accessed during the current operation. the next offset type description 0000h read/write receive/transmit data (port 0) 0002h read/write receive/transmit data (port 1) table 17. i/o mode mapping 0004h write-only txcmd (transmit command) 0006h write-only txlength (transmit length) 0008h read-only interrupt status queue 000ah read/write packetpage pointer 000ch read/write packetpage data (port 0) 000eh read/write packetpage data (port 1) offset type description table 17. i/o mode mapping
76 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet three bits (c, d, and e) are read-only and will al- ways read as 011b. any convenient value may be written to these bits when writing to the packetpage pointer port. the last bit (bit f) indicates whether or not the packetpage pointer should be auto-incre- mented to the next word location. figure 18 shows the structure of the packetpage pointer. 4.10.6 packetpage data ports 0 and 1 the packetpage data ports are used to transfer data to and from any of the CS8900A ? s internal regis- ters. port 0 is used for 16-bit operations and port 0 and 1 are used for 32-bit operations (lower-order word in port 0). 4.10.7 i/o mode operation for an i/o read or write operation, the aen pin must be low, and the 16-bit i/o address on the isa system address bus (sa0 - sa15) must match the address space of the CS8900A. for a read, the ior pin must be low, and for a write, the iow pin must be low. note: the isa latchable address bus (la17 - la23) is not needed for applications that use only i/o mode and receive dma operation. 4.10.8 basic i/o mode transmit i/o mode transmit operations occur in the follow- ing order (using interrupts): 1) the host bids for storage of the frame by writ- ing the transmit command to the txcmd port (i/o base + 0004h) and the transmit frame length to the txlength port (i/o base + 0006h). 2) the host reads the busst register (register 18) to see if the rdy4txnow bit (bit 8) is set. to read the busst register, the host must first set the packetpage pointer at the correct location by writing 0138h to the packetpage pointer port (i/o base + 000ah). it can then read the busst register from the packetpage data port (i/o base + 000ch). if rdy4txnow is set, the frame can be written. if clear, the host must wait for CS8900A buffer memory to become available. if rdy4txie (register b, bufcfg, bit 8) is set, the host will be interrupted when rdy4tx (register c, bufevent, bit 8) becomes set. if the txbiderr bit (register 18, busst, bit 7) is set, the transmit length is not valid. 3) once the CS8900A is ready to accept the frame, the host executes repetitive write in- structions (rep out) to the receive/transmit data port (i/o base + 0000h) to transfer the en- tire frame from host memory to CS8900A memory. for a more detailed description of transmit, see section 5.7 on page 98. 4.10.9 basic i/o mode receive i/o mode receive operations occur in the following order (in this example, interrupts are enabled to signal the presence of a valid receive frame): 1) a frame is received by the CS8900A, triggering an enabled interrupt. 2) the host reads the interrupt status queue port (i/o base + 0008h) and is informed of the re- ceive frame. 3) the host reads the frame data by executing re- petitive read instructions (rep in) from the receive/transmit data port (i/o base + 0000h) to transfer the frame from CS8900A memory to 10 32 5 4 76 packetpage register address 98 ba dc f e i/o base + 000bh i/o base + 000ah bit f: 0 = pointer remains fixed 1 = auto-increments to next word location figure 18. packetpage pointer
ds271pp4 77 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet host memory. preceding the frame data are the contents of the rxstatus register (packetpage base + 0400h) and the rxlength register (pack- etpage base + 0402h). for a more detailed description of receive, see section 5.2 on page 78. 4.10.10 accessing internal registers to access any of the CS8900A ? s internal registers in i/o mode, the host must first setup the pack- etpage pointer. it does this by writing the pack- etpage address of the target register to the packetpage pointer port (i/o base + 000ah). the contents of the target register is then mapped into the packetpage data port (i/o base + 000ch). if the host needs to access a sequential block of reg- isters, the msb of the packetpage address of the first word to be accessed should be set to "1". the packetpage pointer will then move to the next word location automatically, eliminating the need to set- up the packetpage pointer between successive ac- cesses (see figure 18). 4.10.11 polling the CS8900A in i/o mode if interrupts are not used, the host can poll the CS8900A to check if receive frames are present and if memory space is available for transmit.
78 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 5.0 operation 5.1 managing interrupts and servicing the interrupt status queue the interrupt status queue (isq) is used by the CS8900A to communicate event reports to the host processor. whenever an event occurs that triggers an enabled interrupt, the CS8900A sets the appro- priate bit(s) in one of five registers, maps the con- tents of that register to the isq, and drives the selected interrupt request pin high (if an earlier in- terrupt is waiting in the queue, the interrupt request pin will already be high). when the host services the interrupt, it must first read the isq to learn the nature of the interrupt. it can then process the inter- rupt (the first read to the isq causes the interrupt request pin to go low.) three of the registers mapped to the isq are event registers: rxevent (register 4), txevent (register 8), and bufevent (register c). the other two reg- isters are counter-overflow reports: rxmiss (reg- ister 10) and txcol (register 12). there may be more than one rxevent report and/or more than one txevent report in the isq at a time. however, there may be only one bufevent report, one rx- miss report and one txcol report in the isq at a time. event reports stored in the isq are read out in the order of priority, with rxevent first, followed by txevent, bufevent, rxmiss, and then txcol. the host only needs to read from one location to get the interrupt currently at the front of the queue. in memory mode, the isq is located at packetpage base + 0120h. in i/o mode, it is located at i/o base + 0008h. each time the host reads the isq, the bits in the corresponding register are cleared and the next report in the queue moves to the front. when the host starts reading the isq, it must read and process all event reports in the queue. a read- out of a null word (0000h) indicates that all inter- rupts have been read. the isq is read as a 16-bit word. the lower six bits (0 through 5) contain the register number (4, 8, c, 10, or 12). the upper ten bits (6 through f) contain the register contents. the host must always read the entire 16-bit word. the active interrupt pin (intrqx) is selected via the interrupt number register (packetpage base + 22h). as an additional option, all of the interrupt pins can be 3-stated using the same register. see section 4.3 on page 41. an event triggers an interrupt only when the en- ableirq bit of the bus control register (bit f of register 17) is set. after the CS8900A has generat- ed an interrupt, the first read of the isq makes the intrq output pin go low (inactive). intrq re- mains low until the null word (0000h) is read from the isq, or for 1.6us, whichever is longer. 5.2 basic receive operation 5.2.0.1 overview once an incoming packet has passed through the analog front end and manchester decoder, it goes through the following three-step receive process: 1) pre-processing 2) temporary buffering 3) transfer to host figure 20 shows the steps in frame reception. as shown in the figure, all receive frames go through the same pre-processing and temporary buffering phases, regardless of transfer method once a frame has been pre-processed and buffered, it can be accessed by the host in either memory or i/o space. in addition, the CS8900A can transfer receive frames to host memory via host dma. this section describes receive frame pre-processing and memory and i/o space receive operation. section 5.4 on page 89 through section 5.5 on page 92 describe dma operation.
ds271pp4 79 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet an enabled interrupt occurs. the selected interrupt request pin is driven high (active) if not already high. isq = 0000h? yes the host reads the isq. the selected interrupt request pin is driven low. no process applicable rxevent bits: extradata, runt, crcerror, rxok. process applicable txevent bits: 16coll, jabber, out-of-window, txok. process applicable bufevent bits: rxdest, rx128, rxmiss, txunderrun, rdy4tx, rxdmaframe, swint. process rxmiss counter. process txcol counter. which event report type? rxevent txevent bufevent rxmiss txcol none of the above service default exit. interrupts re-enabled. (interrupts will be disabled for at least 1.6 us.) figure 19. interrupt status queue
80 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 5.2.1 terminology: packet, frame, and transfer the terms packet, frame, and transfer are used ex- tensively in the following sections. they are de- fined below for clarity: 5.2.1.1 packet the term "packet" refers to the entire serial string of bits transmitted over an ethernet network. this includes the preamble, start-of-frame delimiter (sfd), destination address (da), source address (sa), length field, data field, pad bits (if neces- sary), and frame check sequence (fcs, also called crc). figure 9 shows the format of a pack- et. 5.2.1.2 frame the term "frame" refers to the portion of a packet from the da to the fcs. this includes the destina- tion address (da), source address (sa), length field, data field, pad bits (if necessary), and frame check sequence (fcs, also called crc). figure 9 shows the format of a frame. the term "frame data" refers to all the data from the da to the fcs that is to be transmitted, or that has been received. 5.2.1.3 transfer the term "transfer" refers to moving data across the isa bus, to and from the CS8900A. during receive operations, only frame data are transferred from the CS8900A to the host (the preamble and sfd are stripped off by the CS8900A ? s mac engine). the fcs may or may not be transferred, depending on the configuration. all transfers to and from the CS8900A are counted in bytes, but may be padded for double word alignment. 5.2.2 receive configuration after each reset, the CS8900A must be configured for receive operation. this can be done automati- cally using an attached eeprom or by writing configuration commands to the CS8900A ? s internal registers (see section 3.4 on page 20). the items that must be configured include: which physical interface to use; which types of frames to accept; which receive events cause interrupts; and, how received frames are transferred. 5.2.2.1 configuring the physical interface configuring the physical interface consists of de- termining which ethernet interface should be ac- tive, and enabling the receive logic for serial reception. this is done via the linectl register (register 13) and is described in table18. 5.2.2.2 choosing which frame types to accept the rxctl register (register 5) is used to deter- mine which frame types will be accepted by the CS8900A (a receive frame is said to be "accepted" when the frame is buffered, either on chip or in host yes no use dma? frame held on chip frame dmaed to host memory host reads frame from host memory frame pre- processed frame temporarily buffered packet received preamble and start-of-frame delimiter removed host reads frame from CS8900A memory figure 20. frame reception
ds271pp4 81 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet memory via dma). table 19 describes the config- uration bits in this register. refer to section 5.3 on page 86 for a detailed description of destination address filtering. 5.2.2.3 selecting which events cause interrupts the rxcfg register (register 3) and the bufcfg register (register b) are used to determine which receive events will cause interrupts to the host pro- cessor. table 21 describes the interrupt enable (ie) bits in these registers. 5.2.2.4 choosing how to transfer frames the rxcfg register (register 3) and the busctl register (register 17) are used to determine how frames will be transferred to host memory, as de- scribed in table 22. register 13, linectl bit bit name operation 6 serrxon when set, reception enabled. 8 auionly when set, aui selected (takes precedence over autoaui/10bt). 9 autoaui/10bt when set, automatic interface selection enabled. when both bits 8 and 9 are clear, 10base-t selected. e lorx squelch when set, receiver squelch level reduced by approximately 6 db. table 18. physical interface configuration register 5, rxctl bit bit name operation 6 iahasha when set, individual address frames that pass the hash filter are accepted*. 7promis cuousa when set, all frames are accepted*. 8 rxoka when set, frames with valid length and crc and that pass the da filter are accepted. 9 multicasta when set, multicast frames that pass the hash filter are accepted*. a individuala when set, frames with da that matches the ia at packetpage base + 0158h are accepted*. bbroad- casta when set, all broadcast frames are accepted*. c crcerrora when set, frames with bad crc that pass the da filter are accepted. d runta when set, frames shorter than 64 bytes that pass the da filter are accepted. e extradataa when set, frames longer than 1518 bytes that pass the da filter are accepted (only the first 1518 bytes are buffered). * must also meet the criteria programmed into bits 8, c, d, and e. table 19. frame acceptance criteria register 3, rxcfg bit bit name operation 8 rxokie when set, there is an interrupt if a frame is received with valid length and crc*. c crcerrorie when set, there is an interrupt if a frame is received with bad crc*. d runtie when set, there is an interrupt if a frame is received that is shorter than 64 bytes*. e extradataie when set, there is an interrupt if a frame is received that is longer than 1518 bytes*. * must also pass the da filter before there is an interrupt. table 20. register b, bufcfg bit bit name operation 7 rxdmaie when set, there is an interrupt if one or more frames are trans- ferred via dma. a rxmissie when set, there is an interrupt if a frame is missed due to insufficient receive buffer space. b rx128ie when set, there is an interrupt after the first 128 bytes of receive data have been buffered. d missovfloie when set, there is an interrupt if the rxmiss counter overflows. f rxdestie when set, there is an interrupt after the da of an incoming frame has been buffered. table 21. registers 3 and b interrupt configuration
82 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 5.2.3 receive frame pre-processing the CS8900A pre-processes all receive frames us- ing a four step process: 1) destination address filtering; 2) early interrupt generation; 3) acceptance filtering; and, 4) normal interrupt generation. figure 21 provides a diagram of frame pre-process- ing. 5.2.3.1 destination address filtering all incoming frames are passed through the desti- nation address filter (da filter). if the frame ? s da passes the da filter, the frame is passed on for fur- ther pre-processing. if it fails the da filter, the frame is discarded. see section 5.3 on page 86 for a more detailed description of da filtering. register 3, rxcfg bit bit name operation 7 streame when set, stream transfer enabled. 9 rxdmaonly when set, dma slave opera- tion used for all receive frames. a autorx dmae when set, auto-switch dma enabled. b buffercrc when set, the received crc is buffered. register 17, busctl bit bit name operation b dmaburst when set, dma operations hold the bus for up to approx- imately 28 s. when clear, dma operations are continu- ous. d rxdmasize when set, dma buffer size is 64 kbytes. when clear, dma buffer size is 16 kbytes. table 22. receive frame pre-processing pass da filter? discard frame destination address filter check: - promiscuousa? - iahasha? - multicasta? - individuala? - broadcasta? receive frame yes no yes no generate interrupts check: - rxokie? - extradataie? - crcerrorie? - runtie? - rxdmaie? pre-processing complete generate early interrupts if enabled (see next figure) acceptance filter check: - rxoka? - extradataa? - runta? - crcerrora? status of receive frame reported in rxevent register, frame discarded. status of receive frame reported in rxevent register, frame accepted into on-chip ram pass accept. filter? figure 21. receive frame pre-processing
ds271pp4 83 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 5.2.3.2 early interrupt generation the CS8900A support the following two early in- terrupts that can be used to inform the host that a frame is being received: rxdest: the rxdest bit (register c, bufevent, bit f) is set as soon as the destination address (da) of the incoming frame passes the da fil- ter. if the rxdestie bit (register b, bufcfg, bit f) is set, the CS8900A generates a corre- sponding interrupt. once rxdest is set, the host is allowed to read the incoming frame's da (the first 6 bytes of the frame). rx128: the rx128 bit (register c, bufevent, bit b) is set as soon as the first 128 bytes of the incoming frame have been received. if the rx128ie bit (register b, bufcfg, bit b) is set, the CS8900A generates a corresponding inter- rupt. once the rx128 bit is set, the rxdest bit is cleared and the host is allowed to read the first 128 bytes of the incoming frame. the rx128 bit is cleared by the host reading the bufevent register (either directly or through the interrupt status queue) or by the CS8900A de- tecting the incoming frame's end-of-frame (eof) sequence. like all event bits, rxdest and rx128 are set by the CS8900A whenever the appropriate event oc- curs. unlike other event bits, rxdest and rx128 may be cleared by the CS8900A without host inter- vention. all other event bits are cleared only by the host reading the appropriate event register, either directly or through the interrupt status queue (isq). (rxdest and rx128 can also be cleared by the host reading the bufevent register, either di- rectly or through the interrupt status queue). fig- ure 22 provides a diagram of the early interrupt process. 5.2.3.3 acceptance filtering the third step of pre-processing is to determine whether or not to accept the frame by comparing the frame with the criteria programmed into the rx- ctl register (register 5). if the receive frame passes the acceptance filter, the frame is buffered, either on chip or in host memory via dma. if the frame fails the acceptance filter, it is discarded. the results of the acceptance filter are reported in the rxevent register (register 4). 5.2.3.4 normal interrupt generation the final step of pre-processing is to generate any enabled interrupts that are triggered by the incom- ing frame. interrupt generation occurs when the en- tire frame has been buffered (up to the first 1518 bytes). for more information about interrupt gener- ation, see section 5.1 on page 78. 5.2.4 held vs. dmaed receive frames all accepted frames are either held in on-chip ram until processed by the host, or stored in host memory via dma. a receive frame that is held in on-chip ram is referred to as a held receive frame. a frame that is stored in host memory via dma is a dmaed receive frame. this section describes buffering and transferring held receive frames. section 5.4 on page 89 through section 5.6 on page 95 describe dmaed receive frames. 5.2.5 buffering held receive frames if space is available, an incoming frame will be temporarily stored in on-chip ram, where it awaits processing by the host. although this re- ceive frame now occupies on-chip memory, the CS8900A does not commit the memory space to it until one of the following two conditions is true: 1) the entire frame has been received and the host has learned about the frame by reading the rx- event register (register 4), either directly or through the isq. or: 2) the frame has been partially received, causing either the rxdest bit (register c, bufevent, bit f) or the rx128 bit (register c, bufevent, bit b) to become set, and the host has learned about
84 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet eof received? 128 bytes received? eof received? 64 bytes received? eof received? receive frame rxdest cleared and runt set. if runta is set, frame accepted and host may read frame. rxdest cleared and rxok or crcerror set, as appropriate. if rxoka or crcerrora is set, frame accepted and host may read frame. rx128 cleared and rxok, crcerror or extradata set, as appropriate. if extradataa, rxoka or crcerrora is set, frame is accepted and host may read frame. da filter passed? yes no yes no no yes yes no no yes rx128 set and rxdest cleared. host may read first 128 received bytes. yes no discard frame rxdest set. host may read the da (first 6 received bytes). figure 22. early interrupt generation
ds271pp4 85 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet the receive frame by reading the bufevent reg- ister (register c), either directly or through the isq. when the CS8900A commits buffer space to a par- ticular held receive frame (termed a committed re- ceived frame), no data from subsequent frames can be written to that buffer space until the frame is freed from commitment. (the committed received frame may or may not have been received error free.) a received frame is freed from commitment by any one of the following conditions: 1) the host reads the entire frame sequentially in the order that it was received (first byte in, first byte out). or: 2) the host reads part or none of the frame, and then issues a skip command by setting the skip_1 bit (register 3, rxcfg, bit 6). or: 3) the host reads part of the frame and then reads the rxevent register (register 5), either direct- ly or through the isq, and learns of another re- ceive frame. this condition is called an "implied skip". ensure that the host does not do ? implied skips. ? both early interrupts are disabled whenever there is a committed receive frame waiting to be processed by the host. 5.2.6 transferring held receive frames the host can read-out held receive frames in mem- ory or i/o space. to transfer frames in memory space, the host executes repetitive move instruc- tions (rep movs) from packetpage base + 0404h. to transfer frames in i/o space, the host ex- ecutes repetitive in instructions (rep in) from i/o base + 0000h, with status and length preceding the frame. there are three possible ways that the host can learn the status of a particular frame. it can: 1) read the interrupt status queue; 2) read the rxevent register directly (register4); or 3) read the rxstatus register (packetpage base + 0400h). 5.2.7 receive frame visibility only one receive frame is visible to the host at a time. the receive frame's status can be read from the rxstatus register (packetpage base + 0400h), and its length can be read from the rxlength reg- ister (packetpage base + 0402h). for more infor- mation about memory space operation, see section 4.9 on page 73. for more information about i/o space operation, see section 4.10 on page 75. 5.2.8 example of memory mode receive opera- tion a common length for short frames is 64 bytes, in- cluding the 4-byte crc. suppose that such a frame has been received with the CS8900A configured as follows: the buffercrc bit (register 3, rxcfg, bit b) is set causing the 4-byte crc to be buffered with the rest of the receive data. the rxoka bit (register 5, rxctl, bit 8) is set, causing the CS8900A to accept good frames (a good frame is one with legal length and valid crc). the rxokie bit (register 3, rxcfg, bit 8) is set, causing an interrupt to be generated when- ever a good frame is received. then the transfer to the host would proceed as fol- lows: 1) the CS8900A generates an rxok interrupt to the host to signal the arrival of a good frame. 2) the host reads the isq (packetpage base +
86 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 0120h) to assess the status of the receive frame and sees the contents of the rxevent register (register 4) with the rxok bit (bit 8) set. 3) the host reads the receive frame ? s length from the rxlength register (packetpage base + 0402h). 4) the host reads the frame data by executing 32 consecutive mov instructions starting with packetpage base + 0404h. the memory map of the 64-byte frame is given in table 23. 5.2.9 receive frame byte counter the receive frame byte counter describes the num- ber of bytes received for the current frame. the counter is incremented in real time as bytes are re- ceived from the ethernet. the byte counter can be used by the driver to determine how many bytes are available for reading out of the CS8900A. maxi- mum ethernet throughput can be achieved by using i/o or memory modes, and by dedicating the cpu to reading this counter, and using the count to read the frame out of the CS8900A at the same time it is being received by the CS8900A from the ethernet (parallel frame-reception and frame-read-out tasks). the byte count register resides at packetpage base + 50h. following an rxdest or rx128 interrupt the regis- ter contains the number of bytes which are avail- able to be read by the cpu. when the end of frame is reached, the count contains the final count value for the frame, including the allowance for the buff- ercrc option. when this final count is read by the cpu the count register is set to zero. therefore to read a complete frame using the byte count register, the register can be read and the data moved until a count of zero is detected. then the rxevent regis- ter can be read to determine the final frame status. the sequence is as follows: 1) at the start of a frame, the byte counter matches the incoming character counter. the byte counter will have an even value prior to the end of the frame. 2) at the end of the frame, the final count, includ- ing the allowance for the crc (if the buffer- crc option is enabled), is held until the byte counter is read. 3) when a read of the byte counter returns a count of zero, the previous count was the final count. the count may now have an odd value. 4) rxevent should be read to obtain a final status of the frame, followed by a skip command to complete the operation. note that all rxevent ? s should be processed before using the byte counter. the byte counter should be used following a bufevent when rxdest or rx128 interrupts are enabled. 5.3 receive frame address filtering the CS8900A is equipped with a destination ad- dress (da) filter used to determine which receive frames will be accepted. (a receive frame is said to be "accepted" by the CS8900A when the frame data are placed in either on-chip memory, or in host memory space word offset description of data stored in on- chip ram 0400h rxstatus register (the host may skip reading 0400h since rxevent was read from the isq.) 0402h rxlength register (in this example, the length is 40h bytes. the frame starts at 0404h, and runs through 0443h.) 0404h to 0409h 6-byte source address. 040ah to 040fh 6-byte destination address. 0410h to 0411h 2-byte length or type field. 0412h to 043fh 46 bytes of data. 0440h crc, bytes 1 and 2 0442h crc, bytes 3 and 4 table 23. example memory map
ds271pp4 87 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet memory by dma). the da filter can be config- ured to accept the following frame types: 5.3.0.1 individual address frames for all individual address frames, the first bit of the da is a "0" (da[0] = 0), indicating that the ad- dress is a physical address. the address filter ac- cepts individual address frames whose da matches the individual address (ia) stored at packetpage base + 0158h, or whose hash-filtered da matches one of the bits programmed into the logical address filter (the hash filter is described later in this section). 5.3.0.2 multicast frames for multicast frames, the first bit of the da is a "1" (da[0] = 1), indicating that the frame is a logical address. the address filter accepts multicast frames whose hash-filtered da matches one of the bits programmed into the logical address filter (the hash filter is described later is this section). as shown in table 25, broadcast frames can be ac- cepted as multicast frames under a very specific set of conditions. 5.3.0.3 broadcast frames frames with da equal to ffff ffff ffffh are broadcast frames. in addition, the CS8900A can be configured for promiscuous mode, in which case it will accept all receive frames, irrespective of da. 5.3.1 configuring the destination address filter the da filter is configured by programming five da filter bits in the rxctl register (register 5): iahasha, promiscuousa, multicasta, individua- la, and broadcasta. four of these bits are associat- ed with four status bits in the rxevent register (register 4): iahash, hashed, individualadr, and broadcast. the rxevent register reports the results of the da filter for a given receive frame. the bits associated with da filtering are summarized be- low: the iahasha, multicasta, individuala, and broadcasta bits are used independently. as a re- sult, many da filter combinations are possible. for example, if multicasta and individuala are set, then all frames that are either multicast or individ- ual address frames are accepted. the promiscu- ousa bit, when set, overrides the other four da bits, and allows all valid frames to be accepted. ta- ble 24 summarizes the configuration options avail- able for da filtering. bit # rxctl register 5 rxevent register 4 6 iahasha iahash (used only if iahasha = 1) 7 promiscuousa 9 multicasta hashed a individuala individualadr (used only if individuala = 1) b broadcasta broadcast (used only if broadcasta = 1) iahasha promiscuousa multicasta individuala broadcasta frames accepted 0 0 0 1 0 individual address frames with da matching the ia at pack- etpage base + 0158h 1 0 0 0 0 individual address frames with da that pass the hash filter (da[0] must be ? 0 ? ) 0 0 1 0 0 multicast frames with da that pass the hash filter (da[0] must be ? 1 ? ) 0 0 0 0 1 broadcast frames x 1 x x x all frames table 24. da filtering options
88 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet it may become necessary for the host to change the destination address (da) filter criteria without re- setting the CS8900A. this can be done as follows: 1) clear serrxon (register 13, linectl, bit 6) to prevent any additional receive frames while the filter is being changed. 2) modify the da filter bits (b, a, 9, 7, and 6) in the rxctl register. modify the logical ad- dress filter at packetpage base + 0150h, if nec- essary. modify the individual address at packetpage base + 0158h, if necessary. 3) set serrxon to re-enable the receiver. because the receiver has been disabled, the CS8900A will ignore frames while the host is changing the da filter. 5.3.2 hash filter the hash filter is used to help determine which multicast frames and which individual address frames should be accepted by the CS8900A. 5.3.2.1 hash filter operation see figure 23. the da of the incoming frame is passed through the crc logic, generating a 32-bit crc value. the six most-significant bits of the crc are latched into the 6-bit hash register (hr). the contents of the hr are passed through a 6-to- 64-bit decoder, asserting one of the decoder ? s out- puts. the asserted output is compared with a corre- sponding bit in the 64-bit logical address filter, located at packetpage base + 0150h. if the decoder output and the logical address filter bit match, the frame passes the hash filter and the hashed bit (register 4, rxevent, bit 9) is set. if the two do not match, the frame fails the filter and the hashed bit is clear. whenever the hash filter is passed by a "good" frame, the rxok bit (register 4, rxevent, bit 8) is set and the bits in the hr are mapped to the hash table index bits (register 4, rxevent, bits a through f). 5.3.3 broadcast frame hashing exception table 25 describes in detail the content of the rx- event register for each output of the hash and ad- dress filters, and describes an exception to normal processing. that exception can occur when the hash-filter broadcast address matches a bit in the logical address filter. to properly account for this exception, the software driver should use the fol- lowing test to determine if the rxevent register contains a normal rxevent (meaning bits e-a are used for extra data, runt, crc error, broadcast and individualadr) or a hash-table rxevent (mean- ing bits f-a contain the hash table index). if bit hashed =0, or bit rxok=0, or (bits f-a = 02h and the destination address is all ones) then rx- event contains a normal rxevent, else rxevent contained a hash rxevent. 64-bit logical address filter (laf) written into packetpage base + 150h 6-to-64 decoder 1 64 CS8900A crc logic destination address (da) from incoming frame 32-bit crc value (msb) (lsb) 6-bit hash register (hr) [hash table index] 64-input or gate to hashed bit figure 23. hash filter operation
ds271pp4 89 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 5.4 receive dma 5.4.1 overview the CS8900A supports a direct interface to the host dma controller allowing it to transfer receive frames to host memory via slave dma. the dma option applies only to receive frames, and not transmit operation. the CS8900A offers three pos- sible receive dma modes: 1) receive-dma-only mode: all receive frames are transferred via dma. 2) auto-switch dma: dma is used only when needed to help prevent missed frames. 3) streamtransfer: dma is used to minimize the number of interrupts to the host. this section provides a description of receive- dma-only mode. section 5.5 on page 92 describes auto-switch dma and section 5.6 on page 95 de- scribes streamtransfer. 5.4.2 configuring the CS8900A for dma opera- tion the CS8900A interfaces to the host dma control- ler through one pair of the dma request/acknowl- edge pins (see section 3.2 on page 17 for a description of the CS8900A ? s dma interface). four 16-bit registers are used for dma operation. these are described in table 26. receive-dma-only mode is enabled by setting the rxdmaonly bit (register 3, rxcfg, bit 9). note: if the rxdmaonly bit and the autorxd- mae bit (register 3, rxcfg, bit a) are both set, then rxdmaonly takes precedence, and the CS8900A is in dma mode for all receive frames. 5.4.3 dma receive buffer size in receive dma mode, the CS8900A stores re- ceived frames (along with their status and length) in a circular buffer located in host memory space. address type of received frame erred frame? passes hash filter? contents of rxevent bits f-a bit 9 hashed bit 8 rxok bit 6 iahash individual address no yes hash table index 1 1 1 no no extradata runt crc error broadcast individual adr 0 1 0 yes don ? t care extradata runt crc error broadcast individual adr 0 0 0 multicast address no yes hash table index 1 1 0 no no extradata runt crc error broadcast individual adr 0 1 0 yes don ? t care extradata runt crc error broadcast individual adr 0 0 0 broad- cast address no yes (note 6) extradata runt crc error broadcast individual adr 1 1 0 (actual value x00010) no yes (note 7) extradata runt crc error broadcast individual adr 0 1 0 no no extradata runt crc error broadcast individual adr 0 1 0 yes don ? t care extradata runt crc error broadcast individual adr 0 0 0 notes: 6. broadcast frames are accepted as multicast frames if and only if all the following conditions are met simultaneously: a) the logical address filter is programmed as: (msb) 0000 8000 0000 0000h (lsb). note that this laf value corresponds to a multicast addresses of both all 1s and 03-00-00-00-00-01. b) the rx control register (register 5) is programmed to accept individuala, multicasta, rxok-only, and the following address filters were enabled: iahasha and broadcasta. 7. not (note 1). table 25. contents of rxevent upon various conditions
90 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet the size of the circular buffer is determined by the rxdmasize bit (register 17, busctl, bit d). when rxdmasize is clear, the buffer size is 16 kbytes. when rxdmasize is set, the buffer is 64 kbytes. it is the host ? s task to locate and keep track of the dma receive buffer ? s base address. the dma start-of-frame register is the only circuit af- fected by this bit. application note: as a result of the pc ar- chitecture, dma cannot occur across a 128k boundary in memory. thus, the dma buffer re- served for the CS8900A must not cross a 128k boundary in host memory if dma operation is de- sired. requesting a 64k, rather than a 16k buffer, increases the probability of crossing a 128k bound- ary. after the driver requests a dma buffer, the driver must check for a boundary crossing. if the boundary is crossed, then the driver must disable dma functionality. 5.4.4 receive-dma-only operation if space is available, an incoming frame is tempo- rarily stored in on-chip ram. when the entire frame has been received, pre-processed, and ac- cepted, the CS8900A signals the dma controller that a frame is to be transferred to host memory by driving the selected dma request pin high. the dma controller acknowledges the request by driv- ing the dma acknowledge pin low. the CS8900A then transfers the contents of the rxstatus register (packetpage base + 0400h) and the rxlength reg- ister (packetpage base + 0402h) to host memory, followed by the frame data. if the dmaburst bit (register 17, busctl, bit b) is clear, the dma request pin remains high until the entire frame is transferred. if the dmaburst bit is set, the dma request pin (dmarq) remains high for approxi- mately 28 ms then goes low for approximately 1.3 ms to give the cpu and other peripherals access to the bus. when the transfer is complete, the CS8900A does the following: updates the dma start-of-frame register (packetpage base + 0026h); updates the dma frame count register (pack- etpage base + 0028h); updates dma byte count register (packetpage base + 002ah); sets the rxdmaframe bit (register c, bufe- vent, bit 7); and, deallocates the buffer space used by the trans- ferred frame. in addition, if the rxdmaie bit (register b, bufcfg, bit 7) is set, a corresponding interrupt oc- curs. when the host processes dmaed frames, it must read the dma frame count register. whenever a receive frame is missed (lost) due to insufficient receive buffer space, the rxmiss counter (register 10) is incremented. a missed re- ceive frame causes the counter to increment in ei- ther dma or non-dma modes. note that when in dma mode, reading the contents of the rxevent register will return 0000h. status packetpage address register description 0024h dma channel number: dma chan- nel number (0, 1, or 2) that defines the dmarq/dmack pin pair used. 0026h dma start of frame: 16-bit value that defines the offset from the dma base address to the start of the most recently transferred received frame. 0028h dma frame count: the lower 12 bits define the number of valid frames transferred via dma since the last read-out of this register. the upper 4 bits are reserved and not applicable. 002ah dma byte count: defines the num- ber of bytes that have been transferred via dma since the last read-out of this register. table 26. receive dma registers
ds271pp4 91 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet information should be obtained from the dma buffer. 5.4.5 committing buffer space to a dmaed frame although a receive frame may occupy space in the host memory ? s circular dma buffer, the CS8900A ? s memory manager does not commit the buffer space to the receive frame until the entire frame has been transferred and the host learns of the frame ? s existence by reading the frame count register (packetpage base + 0028h). when the CS8900A commits dma buffer space to a particular dmaed receive frame (termed a com- mitted received frame), no data from subsequent frames can be written to that buffer space until the committed received frame is freed from commit- ment. (the committed received frame may or may not have been received error free.) a committed dmaed receive frame is freed from commitment by any one of the following condi- tions: 1) the host rereads the dma frame count regis- ter (packetpage base + 0028h). 2) new frames have been transferred via dma, and the host reads the bufevent register (either directly or from the isq) and sees that the rxd- maframe bit is set (this condition is termed an "implied skip"). 3) the host issues a reset-dma command by set- ting the resetrxdma bit (register 17, bus- ctl, bit 6). 5.4.6 dma buffer organization when dma is used to transfer receive frames, the dma start-of-frame register (packetpage base + 0026h) defines the offset from the dma base to the start of the most recently transferred received frame. frames stored in the dma buffer are trans- ferred as words and maintain double-word (32-bit) alignment. unfilled memory space between suc- cessive frames stored in the dma buffer may result from double-word alignment. these "holes" may be 1, 2, or 3 bytes, depending on the length of the frame preceding the hole. 5.4.7 rxdmaframe bit the rxdmaframe bit (register c, bufevent, bit 7) is controlled by the CS8900A and is set whenev- er the value in the dma frame count register is non-zero. the host cannot clear rxdmaframe by reading the bufevent register (register c). table 27 summarizes the criteria used to set and clear rxdmaframe. 5.4.8 receive dma example without wrap- around figure 24 shows three frames stored in host mem- ory by dma without wrap-around. 5.4.9 receive dma operation for rxdma-only mode in an rxdmaonly mode, a system dma moves all the received frames from the on-chip memory to an external 16- or 64-kbyte buffer memory. the received frame must have passed the destination address filter, and must be completely received. usually, the dma receive frame interrupt (rxd- maie, bit 7, register b, bufcfg) is set so that the CS8900A generates an interrupt when a frame is transferred by dma. figure 25 shows how a dma receive frame interrupt is processed. non-stream transfer mode stream transfer mode (see section 5.6) to set rxd- maframe the rxdmaframe bit is set whenever the dma frame count register (packetpage base + 0028h) transitions to non-zero. the rxdmaframe bit is set at the end of a stream transfer cycle. to c l e a r rxdma- frame the dma frame count is zero. the dma frame count is zero. table 27. rxdmaframe bit
92 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet in the interrupt service routine, the bufevent regis- ter (register c), bit rxdma frame (bit 7) indicates that one or more receive frames were transferred using dma. the software driver should maintain a pointer (e.g. pdma_start) that will point to the beginning of a new frame. after the CS8900A is initialized and before any frame is received, pointer pdma_start points to the beginning of the dma buffer memory area. the first read of the dma frame count, cdma, commits the memory covered by the cdma count, and the dma cannot overwrite this committed space until the space is freed. the driver then processes the frames de- scribed by the cdma count and makes a second read of the dma frame count. this second read frees the buffer memory space described by the cdma counter. during the frame processing, the software should advance the pdma_start pointer. at the end of processing a frame, pointer pdma_start should be made to align with a double-word bound- ary. the software remains in the loop until the dma frame count read is zero. 5.5 auto-switch dma 5.5.1 overview the CS8900A supports a unique feature, auto- switch dma, that allows it to switch between memory or i/o mode and receive dma automati- cally. auto-switch dma allows the CS8900A to realize the performance advantages of memory or i/o mode while minimizing the number of missed frames that could result due to slow processing by the host. rxstatus - frame 1 rxlength - frame 1 rxstatus - frame 2 rxlength - frame 2 frame 2 rxstatus - frame 3 rxlength - frame 3 frame 3 dma buffer base address frame 1 dma byte count (packetpage base + 012ah) dma start of frame register (packetpage base + 0126h) points here. "holes" due to double-word alignment figure 24. example of frames stored in dma buffer
ds271pp4 93 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 5.5.2 configuring the CS8900A for auto-switch dma auto-switch dma mode requires the same config- uration as receive-dma-only mode, with one ex- ception: the autorxdmae bit (register 3, rxcfg, bit a) must be set, and the rxdmaonly bit (register 3, rxcfg, bit 9) must be clear (see section 5.4 on page 89, configuring the CS8900A for dma operation). in auto-switch dma mode, the CS8900A operates in non-dma mode if possi- ble, only switching to slave dma if necessary. note that if the autorxdmae bit and the rxdm- aonly bit (register 3, rxcfg, bit 9) are both set, the CS8900A uses dma for all receive frames. 5.5.3 auto-switch dma operation whenever a frame begins to be received in auto- switch dma mode, the CS8900A checks to see if there is enough on-chip buffer space to store a max- imum length frame. if there is, the incoming frame is pre-processed and buffered as normal. if there isn ? t, the CS8900A ? s mac engine compares the frame ? s destination address (da) to the criteria programmed into the da filter. if the incoming da fails the da filter, the frame is discarded. if the da passes the da filter, the CS8900A automatically switches to dma mode and starts transferring the frame(s) currently being held in the on-chip buffer into host memory. this frees up buffer space for the incoming frame. process the c dma frames read the dma frame count (c dma ) (packetpage base + 0028h) no c dma = 0 ? host enters interrupt routine process other events that caused interrupt yes no rxdma frame bit set? process other events that caused interrupt yes figure 25. rxdma only operation
94 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet figure 26 shows the steps the CS8900A goes through in determining when to automatically switch to dma. whenever the CS8900A automatically enters dma, at least one complete frame is already stored in the on-chip buffer. because frames are trans- ferred to the host in the same order as received (first in, first out), the beginning of the received frame that triggered the switch to dma is not the first frame to be transferred. instead, the oldest noncom- mitted frame in the on-chip buffer is the first frame to use dma. when dma begins, any pending rx- event reports in the interrupt status queue are dis- carded because the host cannot process those events until the corresponding frames have been completely dmaed. auto-switch dma works only on entire received frames. the CS8900A does not use auto-switch dma to transfer partial frames. also, when a frame has been committed (see section 5.2.5 on page 83), the CS8900A will not switch to dma mode until the committed frame has been transferred com- pletely or skipped. after a complete frame has been moved to host memory, the CS8900A updates the dma start-of- frame register (packetpage base + 0126h), the dma frame count register (packetpage base + 0128h), and the dma byte count register, then sets the rxdmaframe bit (register c, bufevent, bit 7). if rxdmaie (register b, bufcfg, bit 7) is set, a corresponding interrupt occurs. 5.5.4 dma channel speed vs. missed frames when the CS8900A starts dma, the entire oldest, noncommitted frame must be placed in host mem- ory before on-chip buffer space will be freed for the next incoming frame. if the oldest frame is relative- ly large, and the next incoming frame also large, the incoming frame may be missed, depending on the speed of the dma channel. if this happens, the CS8900A will increment the rxmiss counter (reg- ister 10) and clear any event reports (rxevent and bufevent) associated with the missed frame. 5.5.5 exit from dma when the CS8900A has activated receive dma, it remains in dma mode until all of the following are true: the host processes all rxevent and bufevent reports pending in the isq. all frames use dma yes yes no no yes no no yes frame discarded frame buffered in on-chip ram auto-switch dma disabled packet received auto-switch to dma frame passed the da filter? rxdma only bit=1 more buffer space available? autorxdma bit=1? figure 26. conditions for switching to dma
ds271pp4 95 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet the host reads a zero value from the dma frame count register (packetpage base + 0028h). the CS8900A is not in the process of transfer- ring a frame via dma. 5.5.6 auto-switch dma example figure 27 shows how the CS8900A enters and exits auto-switch dma mode. 5.6 streamtransfer 5.6.1 overview the CS8900A supports an optional feature, streamtransfer, that can reduce the amount of cpu overhead associated with frame reception. streamtransfer works during periods of high re- ceive activity by grouping multiple receive events into a single interrupt, thereby reducing the number of receive interrupts to the host processor. during periods of peak loading, streamtransfer will elim- inate 7 out of every 8 interrupts, cutting interrupt overhead by up to 87%. 5.6.2 configuring the CS8900A for streamtransfer streamtransfer is enabled by setting the streame bit along with either the autorxdmae bit or the rxdmaonly bit in register receiver configuration (register 3). (streamtransfer must not be selected unless either one of autorxdmae or rxdma- only is selected.)streamtransfer only applies to "good" frames (frames of legal length with valid crc). therefore, the rxoka bit and the rxokie bit must both be set. finally, streamtransfer works on whole packets and is not compatible with early interrupts. this requires that the rxdestie bit and the rx128ie bit both be clear. table 28 summarizes how to configure the CS8900A for streamtransfer. 5.6.3 streamtransfer operation when streamtransfer is enabled, the CS8900A will initiate a streamtransfer cycle whenever two or more frames with the following characteristics are received: 1) pass the destination address filter; 2) are of legal length with valid crc; and, 3) are spaced "back-to-back" (between 9.6 and 52 s apart). during a streamtransfer cycle the CS8900A does the following: delays the normal rxok interrupt associated with the first receive frame; switches to receive dma mode; transfers up to eight receive frames into host memory via dma; updates the dma start-of-frame register (packetpage base + 0026h); updates the dma frame count register (pack- etpage base + 0028h); updates dma byte count register (packetpage base + 002ah); sets the rxdmaframe bit (register c, bufe- vent, bit 7); and, generates an rxdmaframe interrupt. 5.6.4 keeping streamtransfer mode active when the CS8900A initiates a streamtransfer cy- cle, it will continue to execute cycles as long as the following conditions hold true: register name bit bit name value register 3, rxcfg 7 streame 1 8rxokie 1 9 or a rxdmaonly or autorxdma 1 or 1 register 5, rxctl 8 rxoka 1 register b, bufcfg 7 rxdmaie 1 frxdestie 0 b rx128ie 0 table 28. stream transfer configuration
96 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet f r a m e 1 f r a m e 2 frame 3 starts to be received and passes the da filter. this activates auto-switch dma. f r a m e 3 frame 1 is placed in host memory via dma freeing space for the incoming frame 3. the CS8900A updates the dma frame count, dma start of frame and dma byte count registers. it then sets the rxdma dmaframe bit and generates an interrupt. frame 2 is placed in host memory via dma and the CS8900A updates the dma registers. the host responds to the rxdmaframe interrupt, and reads the frame count register, which is cleared when read. since there are no receive interrupts pending, the CS8900A exits dma (assumes frame 3 is still coming in). receive dma used during this time. at this point, the CS8900A does not have sufficient buffer space for another complete large frame (1518 bytes). frame 1 received and completely stored in on-chip ram. frame 2 received and completely stored in on-chip ram. enter example here exit example time frame 3 is completely buffered in on-chip ram, and awaits processing by the host. entering this example, the receive buffer is empty and the dma frame count (packetpage base + 0028h) is zero. figure 27. example of auto-switch dma
ds271pp4 97 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet all packets received are of legal length with val- id crc; each packet follows its predecessor by less than 52 ms; and, the da of each packet passes the da filter. if any of these conditions are not met, the CS8900A exits streamtransfer by generating rxok and rxdma interrupts. the CS8900A then returns to either memory, i/o, or dma mode, depending on configuration. 5.6.5 example of streamtransfer figure 28 shows how four back-to-back frames, followed by five back-to-back frames, would be re- ceived without streamtransfer. figure 29 shows how the same sequence of frames would be re- ceived with streamtransfer. 5.6.6 receive dma summary table 29 summarize the receive dma configura- tion options supported by the CS8900A. 4 back-to-back frames 5 back-to-back frames interrupt request 9 interrupts for 9 "good" packets time t > 52 us figure 28. receive example without stream transfer 4 back-to-back frames 5 back-to-back frames interrupt request 2 interrupts for 9 "good" packets time t > 52 us figure 29. receive dma configuration options rxdmaonly (register 3, rxcfg,bit 9) autorxdmaie (register 3, rxcfg, bit a) rxdmaie (register b, bufcfg, bit 7) rxokie (register 3, rxcfg, bit 8) CS8900A configuration 1 na 0 na receive dma used for all receive frames, without interrupts. 1 na 1 na receive dma used for all receive frames, with bufevent interrupts. 0 1 0 0 auto-switch dma used if necessary, without inter- rupts. 0 1 1 1 auto-switch dma used if necessary, with rxevent and bufevent interrupts possible. 0 0 na na memory or i/o mode only. table 29. receive dma configuration options
98 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 5.7 transmit operation 5.7.1 overview packet transmission occurs in two phases. in the first phase, the host moves the ethernet frame into the CS8900A ? s buffer memory. the first phase be- gins with the host issuing a transmit command. this informs the CS8900A that a frame is to be transmitted and tells the chip when (i.e. after 5, 381, or 1021 bytes have been transferred or after the full frame has been transferred to the CS8900A) and how the frame should be sent (i.e. with or with- out crc, with or without pad bits, etc.). the host follows the transmit command with the transmit length, indicating how much buffer space is re- quired. when buffer space is available, the host writes the ethernet frame into the CS8900A ? s inter- nal memory, using either memory or i/o space. in the second phase of transmission, the CS8900A converts the frame into an ethernet packet then transmits it onto the network. the second phase be- gins with the CS8900A transmitting the preamble and start-of-frame delimiter as soon as the proper number of bytes has been transferred into its trans- mit buffer (5, 381, 1021 bytes or full frame, de- pending on configuration). the preamble and start- of-frame delimiter are followed by the data trans- ferred into the on-chip buffer by the host (destina- tion address, source address, length field and llc data). if the frame is less than 64 bytes, in- cluding crc, the CS8900A adds pad bits if config- ured to do so. finally, the CS8900A appends the proper 32-bit crc value. 5.7.2 transmit configuration after each reset, the CS8900A must be configured for transmit operation. this can be done automati- cally using an attached eeprom, or by writing configuration commands to the CS8900A ? s internal registers (see section 3.4 on page 20). the items that must be configured include which physical in- terface to use and which transmit events cause in- terrupts. 5.7.2.1 configuring the physical interface configuring the physical interface consists of de- termining which ethernet interface should be ac- tive (10base-t or aui), and enabling the transmit logic for serial transmission. configuring the phys- ical interface is accomplished via the linectl reg- ister (register 13) and is described in table 30. note that the CS8900A transmits in 10base-t mode when no link pulses are being received only if bit disablelt is set in register test control (reg- ister 19). 5.7.2.2 selecting which events cause interrupts the txcfg register (register 7) and the bufcfg register (register b) are used to determine which transmit events will cause interrupts to the host pro- cessor. tables 31 and 32 describe the interrupt en- able (ie) bits in these registers. 5.7.3 changing the configuration when the host configures these registers it does not need to change them for subsequent packet trans- missions. if the host does choose to change the tx- cfg or bufcfg registers, it may do so at any time. the effects of the change are noticed immediately. that is, any changes in the interrupt enable (ie) bits may affect the packet currently being transmit- ted. register 13, linectl bit bit name operation 7 sertxon when set, transmission enabled. 8 auionly when set, aui selected (takes precedence over autoaui/10bt). when clear, 10base-t selected. 9 autoaui/10bt when set, automatic interface selection enabled. bmod backoffe when set, the modified backoff algorithm is used. when clear, the standard backoff algorithm is used. d2-part defdis when set, two-part deferral is disabled. table 30. physical interface configuration
ds271pp4 99 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet if the host chooses to change bits in the linectl register after initialization, the modbackoffe bit and any receive related bit (lorxsquelch, serrx- on) may be changed at any time. however, the auto aui/10bt and auionly bits should not be changed while the sertxon bit is set. if any of these three bits are to be changed, the host should first clear the sertxon bit (register 13, linectl, bit 7), and then set it when the changes are com- plete. 5.7.4 enabling crc generation and padding whenever the host issues a transmit request com- mand, it must indicate whether or not the cyclic redundancy check (crc) value should be ap- pended to the transmit frame, and whether or not pad bits should be added (if needed). table 33 de- scribes how to configure the CS8900A for crc generating and padding. 5.7.5 individual packet transmission whenever the host has a packet to transmit, it must issue a transmit request to the CS8900A consist- ing of the following three operations in the exact order shown: 1) the host must write a transmit command to the txcmd register (packetpage base + 0144h). the contents of the txcmd register may be read back from the txcmd register (register 9). 2) the host must write the frame ? s length to the txlength register (packetpage base + 0146h). 3) the host must read the busst register (regis- ter 18) the information written to the txcmd register tells the CS8900A how to transmit the next frame. register 7, txcfg bit bit name operation 6 loss-of- crsie when set, there is an interrupt whenever the CS8900A fails to detect carrier sense after trans- mitting the preamble (applies to the aui only). 7 sqerrorie when set, there is an interrupt whenever there is an sqe error. 8 txokie when set, there is an interrupt whenever a frame is transmitted successfully.. 9out-of- windowie when set, there is an interrupt whenever a late collision is detected. a jabberie when set, there is an interrupt whenever there is a jabber condi- tion. b anycollie when set, there is an interrupt whenever there is a collision. f 16collie when set, there is an interrupt whenever the CS8900A attempts to transmit a single frame 16 times. table 31. transmitting interrupt configuration register b, bufcfg bit bit name operation 8 rdy4txie when set, there is an interrupt whenever buffer space becomes available for a transmit frame (used with a transmit request). 9 txunder runie when set, there is an interrupt whenever the CS8900A runs out of data after transmit has started. ctxcol ovfloie when set, there is an interrupt whenever the txcol counter overflows. table 32. transmit interrupt configuration register 9, txcmd inhibit crc (bit c) txpad dis (bit d) operation 0 0 pad to 64 bytes if necessary (including crc). 1 0 send a runt frame if specified length less than 60 bytes. 0 1 pad to 60 bytes if necessary (with- out crc). 1 1 send runt if specified length less than 64. the CS8900A will not transmit a frame that is less than 3 bytes. table 33. crc and paddling configuration
100 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet the bits that must be programmed in the txcmd register are described in table 34. for each individual packet transmission, the host must issue a complete transmit request. further- more, the host must write to the txcmd register before each packet transmission, even if the con- tents of the txcmd register does not change. the transmit request described above may be in either memory space or i/o space. 5.7.6 transmit in poll mode in poll mode, rdy4txie bit (register b, bufcfg, bit 8) must be clear (interrupt disabled). the trans- mit operation occurs in the following order and is shown in figure 30. 1) the host bids for frame storage by writing the transmit command to the txcmd register (memory base+ 0144h in memory mode and i/o base + 0004h in i/o mode). 2) the host writes the transmit frame length to the txlength register (memory base + 0146h in memory mode and i/o base + 0006h in i/o mode). if the transmit length is erroneous, the command is discarded and the txbiderr bit (register 18, busst, bit 7) is set. 3) the host reads the busst register. this read is performed in memory mode by reading regis- ter 18, at memory base + 0138h. in i/o mode, the host must first set the packetpage pointer at the correct location by writing 0138h to the packetpage pointer port (i/o base + 000ah). the host can then read the busst register from the packetpage data port (i/o base + 000ch). 4) after reading the register, the rdy4txnow bit (bit 8) is checked. if the bit is set, the frame can be written. if the bit is clear, the host must con- tinue reading the busst register (register 18) and checking the rdy4txnow bit (bit 8) until the bit is set. when the CS8900A is ready to accept the frame, the host transfers the entire frame from host mem- ory to CS8900A memory using ? rep ? instruction (rep movs starting at memory base + 0a00h in memory mode, and rep out to receive/transmit data port (i/o base + 0000h) in i/o mode). 5.7.7 transmit in interrupt mode in interrupt mode, rdy4txie bit (register b, bufcfg, bit 8) must be set for transmit operation. transmit operation occurs in the following order and is shown in figure 31. 1) the host bids for frame storage by writing the transmit command to the txcmd register (memory base + 0144h in memory mode and i/o base + 0004h in i/o mode). 2) the host writes the transmit frame length to the txlength register (memory base + 0146h in memory mode and i/o base + 0006h in i/o register 9, txcmd bit bit name operation 67 tx start clear clear start preamble after 5 bytes have been transferred to the CS8900A. clear set start preamble after 381 bytes have been trans- ferred to the CS8900A. set clear start preamble after 1021 bytes have been trans- ferred to the CS8900A. set set start preamble after entire frame has been transferred to the CS8900A. 8 force when set, the CS8900A dis- cards any frame data cur- rently in the transmit buffer. 9 onecoll when set, the CS8900A will not attempt to retransmit any packet after a collision. c inhibitcrc when set, the CS8900A does not append the 32-bit crc value to the end of any transmit packet. d txpaddis when set, the CS8900A will not add pad bits to short frames. table 34. tx command configuration
ds271pp4 101 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet mode). if the transmit length is erroneous, the command is discarded and the txbiderr, bit 7, in busst register is set. 3) the host reads the busst register. this read is performed in memory mode by reading regis- ter 18, at memory base + 0138h. in i/o mode, the host must first set the packetpage pointer at CS8900A commits buffer space to transmit frame host reads the busst register (register 18) transmit request host writes transmit frame to CS8900A host writes transmit command to the txcmd register host writes transmit frame length to the txlength register exit transmit process yes no enter packet transmit process rdy4 txnow bit = 1? polling loop no yes is txcmd pending? exit: can ? t issue command note: issuing a command at this point will cause previous transmit frame to be lost. CS8900A transmits frame figure 30. transmit operation in polling mode
102 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet the correct location by writing 0138h to the packetpage pointer port (i/o base + 000ah), it than can read the busst register from the pack- etpage data port (i/o base + 000ch).after reading the register, the rdy4txnow bit is checked. if the bit is set, the frame can be writ- ten to CS8900A memory. if rdy4txnow is clear, the host will have to wait for the CS8900A buffer memory to become available at which time the host will be interrupted. on interrupt, the host enters the interrupt service routine and reads isq register (memory base + 0120h in memory mode and i/o base + 0008h in i/o) and checks the rdy4tx bit (bit 8). if rdy4tx is clear then the CS8900A waits for the next interrupt. if rdy4tx is set, then the CS8900A is ready to accept the frame. 4) when the CS8900A is ready to accept the frame, the host transfers the entire frame from host memory to CS8900A memory using rep instruction (rep movs to memory base + 0a00h in memory mode, and rep out to re- ceive/transmit data port (i/o base + 0000h) in i/o mode). 5.7.8 completing transmission when the CS8900A successfully completes trans- mitting a frame, it sets the txok bit (register 8, txevent, bit 8). if the txokie bit (register 7, tx- cfg, bit 8) is set, the CS8900A generates a corre- sponding interrupt. 5.7.9 rdy4txnow vs. rdy4tx the rdy4txnow bit (register 18, busst, bit 8) is used to tell the host that the CS8900A is ready to accept a frame for transmission. this bit is used during the transmit request process or after the transmit request process to signal the host that space has become available when interrupts are not being used (i.e. the rdy4txie bit (register b, bufcfg, bit 8) is not set). also, the rdy4tx bit is used with interrupts and requires the rdy4txie bit be set. figure 30 provides a diagram of error free trans- mission without collision. 5.7.10 committing buffer space to a transmit frame when the host issues a transmit request, the CS8900A checks the length of the transmit frame to see if there is sufficient on-chip buffer space. if there is, the CS8900A sets the rdy4txnow bit. if not, and the rdy4txie bit is set, the CS8900A waits for buffer space to free up and then sets the rdy4tx bit. if rdy4txie is not set, the CS8900A sets the rdy4txnow bit when space becomes available. even though transmit buffer space may be avail- able, the CS8900A does not commit buffer space to a transmit frame until all of the following are true: 1) the host must issues a transmit request; 2) the transmit request must be successful; and, 3) either the host reads that the rdy4txnow bit (register 18, busst, bit 8) is set, or the host reads that the rdy4tx bit (register c, bufe- vent, bit 8) is set. if the CS8900A commits buffer space to a particu- lar transmit frame, it will not allow subsequent frames to be written to that buffer space as long as the transmit frame is committed. after buffer space is committed, the frame is sub- sequently transmitted unless any of the following occur: 1) the host completely writes the frame data, but transmission failed on the ethernet line. there are three such failures, and these are indicated by three transmit error bits in the txevent reg- ister (register 8): 16coll, jabber, or out-of- window. or: 2) the host aborts the transmission by setting the force (register 9, txcmd, bit 8) bit. in this case, the committed transmit frame, as well as
ds271pp4 103 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet any yet-to-be-transmitted frames queued in the on-chip memory, are cleared and not transmit- ted. the host should make txlength = 0 when using the force bit. or: 3) there is a transmit under-run, and the tx- underrun bit (register c, bufevent, bit 9) is set. successful transmission is indicated when the txok bit (register 8, txevent, bit 8) is set. CS8900A commits buffer space to transmit frame host reads isq host reads the busst register (register 18) transmit request host writes transmit frame to CS8900A host writes transmit command to the txcmd register host writes transmit frame length to the txlength register rdy4tx bit = 1? exit transmit process no yes no yes rdy4 txnow bit = 1? host enters interrupt routine exit wait-for-interrupt process other events that caused interrupt no yes is txcmd pending? exit: can ? t issue command note: issuing a command at this point will cause previous transmit frame to be lost. enter packet transmit process CS8900A transmits frame figure 31. transmit operation in interrupt mode
104 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 5.7.11 transmit frame length the length of the frame transmitted is determined by the value written into the txlength register (packetpage base + 0146h) during the transmit request. the length of the transmit frame may be modified by the configuration of the txpaddis bit (register 9, txcmd, bit d) and the inhibitcrc bit (register 9, txcmd, bit c). table 35 defines how these bits affect the length of the transmit frame. in addition, it shows which frames the CS8900A will send. 5.8 full duplex considerations the driver should not bid to transmit a long frame (i.e., a frame greater than 118 bytes) if the prior transmit frame is still being transmitted. the end of the transmission of this prior frame is indicated by a txok bit being set in the txevent register (reg- ister 8). 5.9 auto-negotiation considerations when the CS8900A is connected to an auto negoti- ation hub, and if auto-media detection is selected (bits 8 and 9 of register 13), then the CS8900A may not auto-select the 10base-t media. the cause of this situation is described in the following para- graphs. the original ieee 802.3 specification requires the mac to wait until 4 valid link-pulses are received before asserting link-ok. any time an invalid link-pulse is received, the count is restarted. when auto-negotiation occurs, a transmitter sends flps (auto-negotiation fast link pulses) bursts instead of the original ieee 802.3 nlp (normal link pulses). if the hub is attempting to auto-negotiate with the CS8900A, the CS8900A will never get more than 1 "valid" link pulse (valid nlp). this is not a prob- lem if the CS8900A is already sending link-pulses, because when the hub receives nlps from the CS8900A, the hub is required to stop sending flps and start sending nlps. the nlp transmitted by the hub will put the CS8900A into link-ok. however, if the CS8900A is in auto-switch mode, the CS8900A will never send any link-pulses, and the hub will never change from sending flps to sending nlps. register 9, txcmd host specified transmit length at 0146h (in bytes) txpad- dis (bit d) inhibitcrc (bit c) 3 < txlength < 60 60 < txlength < 1514 1514 < txlength < 1518 txlength > 1518 0 0 pad to 60 and add crc send frame and add crc [normal mode] will not send will not send 0 1 pad to 60 and send without crc send frame without crc send frame without crc will not send 1 0 send without pads, and add crc send frame and add crc will not send will not send 1 1 send without pads and without crc send frame without crc send frame without crc will not send notes: 8. if the txpaddis bit is clear and inhibitcrc is set and the CS8900A is commanded to send a frame of length less than 60 bytes, the CS8900A pads. 9. the CS8900A will not send a frame with txlength less than 3 bytes. table 35. transmit frame length
ds271pp4 105 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 6.0 test modes 6.0.1 loopback & collision diagnostic tests internal and external loopback and collision tests can be used to verify the CS8900A ? s functionality when configured for either 10base-t or aui op- eration. 6.0.2 internal tests internal tests allow the major digital functions to be tested, independent of the analog functions. during these tests, the manchester encoder is connected to the decoder. all digital circuits are operational, and the transmitter and receiver are disabled. 6.0.3 external tests external test modes allow the complete chip to be tested without connecting it directly to an ethernet network. 6.0.4 loopback tests during loopback tests, the internal carrier sense (crs) signal, used to detect collisions, is ignored, allowing packet reception during packet transmis- sion. 6.0.5 10base-t loopback and collision tests 10base-t loopback and collision tests are con- trolled by two bits in the test control register: fdx (register 19, testctl, bit e) and ende- cloop (register 19, testctl, bit 9). table 36 de- scribes these tests. 6.0.6 aui loopback and collision tests aui loopback and collision tests are controlled by two bits in the test control register: auiloop (register 19, testctl, bit a) and endecloop (register 19, testctl, bit 9). table 37 describes these tests. test mode fdx endecloop description of test 10base-t inter- nal loopback 1 1 transmit a frame and verify that the frame is received without error. 10base-t inter- nal collision 0 1 transmit frames and verify that collisions are detected and that the internal counters function properly. after 16 collisions, verify that 16coll (register 8, txevent, bit f) is set. 10base-t external loop- back 1 0 connect txd+ to rxd+ and txd- to rxd-. transmit a frame and verify that the frame is received without error. 10base-t external collision 0 0 connect txd+ to rxd+ and txd- to rxd-. transmit frames and verify that collisions are detected and that internal counters function properly. after 16 collisions, verify that 16coll (register 8, txevent, bit f) is set. table 36. 10base-t loopback and collision tests test mode auiloop endecloop description of test aui internal loopback 1 1 transmit a frame and verify that the frame is received without error. aui external loopback 1 0 connect do+ to di+ and do- to di-. transmit a frame and verify that the frame is received without error (since there is no collision signal, an sqe error will occur). aui collision 0 0 start transmission and observe do+/do- activity. input a 10 mhz sine wave to cl+/cl- pins and observe collisions. table 37. aui loopback and collision tests
106 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 6.1 boundary scan boundary scan test mode provides an easy and ef- ficient board-level test for verifying that the CS8900A has been installed properly. boundary scan will check to see if the orientation of the chip is correct, and if there are any open or short circuits. boundary scan is controlled by the test pin. when test is high, the CS8900A is configured for normal operation. when test is low, the fol- lowing occurs: the CS8900A enters boundary scan test mode and stays in this mode as long as test is low; the CS8900A goes through an internal reset and remains in internal reset as long as test is low; the aen pin, normally the isa bus address enable, is redefined to become the boundary scan shift clock input; and all digital outputs and bi-directional pins are placed in a high-impedance state (this electri- cally isolates the CS8900A digital outputs from the rest of the circuit board). for boundary scan to be enabled, aen must be low before test is driven low. a complete boundary scan test is made up of two separate cycles. the first cycle, known as the out- put cycle, tests all digital output pins and all bi-di- rectional pins. the second cycle, known as the input cycle, tests all digital input pins and all bi-di- rectional pins. 6.1.1 output cycle during the output cycle, the falling edge of aen causes each of the 17 digital output pins and each of the 17 bi-directional pins to be driven low, one at a time. the cycle begins with linkled and ad- vances in order counterclockwise around the chip through all 34 pins. this test is referred to as a "walking 0" test. the following is a list of output pins and bi-direc- tional pins that are tested during the output cycle: the output pins not included in this test are: 6.1.2 input cycle during the input cycle, the falling edge of aen causes the state of each selected pin to be trans- ferred to eedataout (that is, eedataout will be high or low depending on the input level of the se- lected pin). this cycle begins with sleep and ad- vances clockwise through each of 33 input pins (all digital input pins except for aen) and each of the 17 bi-directional pins, one pin at a time. the following is a list of input pins and bi-direc- tional pins that are tested during the input cycle: pin name pin # pin name pin # elcs 2 intrq1 31 eecs 3 intrq0 32 eesk 4 iocs16 33 eedataout 5 memcs16 34 dmarq2 11 intrq3 35 dmarq1 13 iochrdy 64 dmarq0 15 sd0 - sd7 65-68, 71-74 csout 17 bstatus 78 sd08-sd15 27-24, 21-18 linkled 99 intrq2 30 lanled 100 table 38. pin name pin # pin name pin # do+ 83 txd- 88 do- 84 res 93 txd+ 87 xtal2 98 table 39. pin name pin # pin name pin # elcs 2 sbhe 36 eedatain 6 sa0 - sa11 37-48 chipsel 7 refresh 49 dmack2 12 sa12 - sa19 50-54, 58-60 dmack1 14 ior 61 dmack0 16 iow 62 sd08-sd15 27-24, 21-18 sd0 - sd7 65-68, 71-74 memw 28 reset 75 memr 29 sleep 77 table 40.
ds271pp4 107 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet the input pins not included in this test are: after the input cycle is complete, one more cycle of aen returns all digital output pins and bi-direc- tional pins to a high-impedance state. 6.1.3 continuity cycle the combination of a complete output cycle, a complete input cycle, and an additional aen cycle is called a continuity cycle. each continuity cycle lasts for 85 aen clock cycles. the first continuity cycle can be followed by additional continuity cycles by keeping test low and continuing to cy- cle aen. when test is driven high, the CS8900A exits boundary scan mode and aen is again used as the isa-bus address enable. figure 32 shows a complete boundary scan conti- nuity cycle. figure 33 shows boundary scan timing. pin name pin # pin name pin # aen 63 cl- 82 test 76 rxd+ 91 dl+ 79 rxd- 92 dl- 80 xtal1 97 cl+ 81 table 41.
108 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet enter boundary scan: CS8900A resets, all digital output pins and bi-directional pins enter high-z state, and aen becomes shift clock aen switches high output cycle aen switches low selected output goes low aen switches high 34 cycles input cycle aen switches low selected input copied out to the eedataout pin aen switches high 50 cycles all digital output pins and bi-directional pins enters high-z state test switches low (aen must be low) not in boundary scan test mode aen switches low aen switches high exit boundary scan: aen becomes isa bus address enable test switches high figure 32. boundary scan continuity cycle
ds271pp4 109 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet testsel aen outputs all outputs tri-state lanled low bstatus low eedataout reset copied out elcs copied out outputs hi z output test 34 clocks input test 50 clocks outputs hi z 1 clock complete continuity cycle 85 clocks linkled low sleep copied out figure 33. boundary scan timing
110 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 7.0 characteristics/specifications - commercial 7.1 absolute maximum ratings (avss, dvss = 0 v, all voltages with respect to 0 v.) warning: normal operation is not guaranteed at these extremes. 7.2 recommended operating conditions (avss, dvss = 0 v, all voltages with respect to 0 v.) 7.3 dc characteristics (t a = 25 c; vdd = 5.0 v or vdd = 3.3v) notes: 1. with digital outputs connected to cmos loads. parameter symbol min max unit power supply digital analog d v dd a v dd -0.3 -0.3 6.0 6.0 v v input current (except supply pins) - 10.0 ma analog input voltage -0.3 ( a v dd +) + 0.3 v digital input voltage -0.3 ( d v dd ) + 0.3 v ambient temperature (power applied) -55 +125 c storage temperature -65 +150 c parameter symbol min max unit 5.0v power supply CS8900A-cq & -iq digital analog d v dd a v dd 4.75 4.75 5.25 5.25 v v 3.3v power supply CS8900A-cq3 & -iq3 digital analog d v dd a v dd 3.135 3.135 3.465 3.465 v v operating ambient temperature CS8900A-cq & -cq3 t a 0+70 c operating ambient temperature CS8900A-iq & -iq3 t a -40 +85 c parameter symbol min max unit crystal (when using external clock - square wave) xtal1 input low voltage v ixh -0.5 0.4 v xtal1 input high voltage v ixh 3.5 d v dd + 0.5 v xtal1 input low current i ixl -40 - a xtal1 input high current i ixh -40a power supply power supply current while active 5.0v i dd -55ma power supply current while active 3.3v i dd -45ma hardware standby mode current (note 1) i ddstndby -1.0ma hardware suspend mode current (note 1) i ddhwsus -100a software suspend mode current (note 1) i ddswsus -1.0ma
ds271pp4 111 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet dc characteristics (continued) notes: 2. od24: open drain output with 24 ma drive od10: open drain output with 10 ma drive b24: bi-directional with 3-state output and 24 ma drive b4w: bi-directional with 3-state output, internal weak pullup, and 4 ma drive o24ts: 3-state output with 24 ma drive o4: output with 4 ma drive i: input iw: input with internal weak pullup parameter symbol min typ max unit digital inputs and outputs (note 2) output low voltage i ol = 24 ma od24, b24, o24ts i ol = 10 ma od10 i ol = 4 ma b4w, o4 v ol - - - - - - 0.4 0.4 0.4 v v v output low voltage (all outputs) v dd = 3.3v and t a = >70 cv ol 0.425 v output high voltage i oh = -12 ma b24 i oh = -2 ma b4w, o24ts, o4 v oh 2.4 2.4 - - - - v v output leakage current 0 v out v cc od24, od10, b24, o24ts b4w i ll -10 -20 - - 10 10 a input low voltage i, iw v il --0.8v input high voltage i, iw v ih 2.4 - - v input leakage current 0 v in v cc i iw i l -10 -20 - - 10 10 a 10base-t interface transmitter differential output voltage (peak) v od 2.2 - 2.8 v receiver normal squelch level (peak) v isq 300 - 525 mv receiver low squelch level (lorxsquelch bit set) v sql 125 - 290 mv aui interface transmitter differential output voltage (do+/do- peak) v aod 0.45 - 1.2 v transmitter undershoot voltage v aodu --100mv transmitter differential idle voltage (do+/do- peak) v idle --40mv receiver squelch level (di+/di- peak) v aisq 180 - 300 mv
112 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 7.4 switching characteristics (t a = 25 c; v dd = 5.0 v or vdd = 3.3v) parameter symbol min typ max unit 16-bit i/o read, iochrdy not used address, aen, sbhe active to iocs16 low t ior1 - - 35 ns address, aen, sbhe active to ior active t ior2 10 - - ns ior low to sd valid t ior3 --135ns address, aen, sbhe hold after ior inactive t ior4 0- -ns ior inactive to active t ior5 35 - - ns ior inactive to sd 3-state t ior6 -30-ns 16-bit i/o read, with iochrdy ior active to iorchrdy inactive t ior7 -30-ns iochrdy low pulse width t ior8 125 - 175 ns iochrdy active to sd valid t ior9 --0ns sa [15:0], aen, sbhe valid address iocs16 in direction: in or out of chip ior sd [15:0] valid data out in out t ior1 t ior2 t ior3 t ior4 t ior5 t ior6 figure 34. 16-bit i/o read, iochrdy not used sa [15:0], aen, sbhe valid address iocs16 in direction: in or out of chip ior sd [15:0] valid data out in out iochrdy out t ior7 t ior8 t ior9 figure 35. 16-bit i/o read, with iochrdy
ds271pp4 113 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet switching characteristics (continued) parameter symbol min typ max unit 16-bit memory read, iochrdy not used sa [19:0], sbhe , chipsel , active to memcs16 low t memr1 - - 30 ns address, sbhe , chipsel active to memr active t memr2 10 - - ns memr low to sd valid t memr3 --135ns address, sbhe , chipsel hold after memr inactive t memr4 0- -ns memr inactive to sd 3-state t memr5 -30-ns memr inactive to active t memr6 35 - - ns 16-bit memory read, with iochrdy memr low to iochrdy inactive t memr7 -35-ns iochrdy low pulse width t memr8 125 - 175 ns iochrdy active to sd valid t memr9 --0ns sa [19:0], sbhe, chipsel valid address memcs16 in direction: in or out of chip memr sd [15:0] valid data out in out t memr1 t memr2 t memr3 t memr4 t memr5 t memr6 figure 36. 16-bit memory read, iochrdy not used sa [19:0], sbhe, chipsel valid address memcs16 in direction: in or out of chip memr sd [15:0] valid data out in out iochrdy out t memr7 t memr8 t memr9 figure 37. 16-bit memory read, with iochrdy
114 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet switching characteristics (continued) parameter symbol min typ max unit dma read dmackx active to ior active t dmar1 60 - - ns aen active to ior active t dmar2 10 - - ns ior active to data valid t dmar3 --135ns ior inactive to sd 3-state t dmar4 -30-ns ior n-1 high to dmarqx inactive t dmar5 - - 20 ns dmackx , aen hold after ior high t dmar6 20 ns 16-bit i/o write address, aen, sbhe valid to iocs16 low t iow1 - - 35 ns address, aen, sbhe valid to iow low t iow2 20 - - ns iow pulse width t iow3 110 - - ns sd hold after iow high t iow4 0- -ns iow low to sd valid t iow5 - - 10 ns iow inactive to active t iow6 35 - - ns address hold after iow high t iow7 0- -ns direction: in or out of chip sd[15:0] out ior dmarqx out in dmackx in aen in t dma1 ior n ior n-1 t dma2 valid data valid data valid data t dma3 t dma5 t dma4 t dma6 figure 38. 16-bit dma read figure 39. 16-bit i/o write sa [15:0], aen, sbhe valid address iocs16 in direction: in or out of chip iow sd [15:0] valid data in out in in t iow1 t iow2 t iow3 t iow4 t iow5 t iow6 t iow7
ds271pp4 115 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet switching characteristics (continued) parameter symbol min typ max unit 16-bit memory write address, sbhe , chipsel valid to memcs16 low t memw1 - - 30 ns address, sbhe , chipsel valid to memw low t memw2 20 - - ns memw pulse width t memw3 110 - - ns memw low to sd valid t memw4 - - 40 ns sd hold after memw high t memw5 0- -ns address hold after memw inactive t memw6 0- -ns memw inactive to active t memw7 35 - - ns 10base-t transmit txd pair jitter into 100 ? load t ttx1 --8ns txd pair return to 50 mv after last positive transition t ttx2 --4.5s txd pair positive hold time at end of packet t ttx3 250 - - ns sa [19:0], sbhe, chipsel valid address memcs16 in direction: in or out of chip memw sd [15:0] valid data in out in in t memw3 t memw4 t memw5 t memw6 t memw7 t memw2 t memw1 figure 40. 16-bit memory write txd t ttx1 t ttx3 t ttx2 figure 41. 10base-t transmit
116 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet switching characteristics (continued) parameter symbol min typ max unit 10base-t receive allowable received jitter at bit cell center t trx1 - - 13.5 ns allowable received jitter at bit cell boundary t trx2 - - 13.5 ns carrier sense assertion delay t trx3 -540-ns invalid preamble bits after assertion of carrier sense t trx4 1-2bits carrier sense deassertion delay t trx5 -270-ns 10base-t link integrity first transmitted link pulse after last transmitted packet t ln1 81624ms time between transmitted link pulses t ln2 81624ms width of transmitted link pulses t ln3 60 100 200 ns minimum received link pulse separation t ln4 2-7ms maximum received link pulse separation t ln5 25 - 150 ms last receive activity to link fail (link loss timer) t ln6 50 - 150 ms t trx3 rxd t trx5 t trx4 t trx1 t trx2 carrier sense (internal) figure 42. 10base-t receive rxd linkled txd t ln1 t ln2 t ln3 t ln4 t ln5 t ln6 figure 43. 10base-t link integrity
ds271pp4 117 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet switching characteristics (continued) parameter symbol min typ max unit aui transmit do pair rise and fall times t atx1 --5ns do pair jitter at bit cell center t atx2 --0.5ns do pair positive hold time at start of idle t atx3 200 - - ns do pair return to 40 mvp after last positive transition t atx4 --8.0s aui receive di pair rise and fall time t arx1 - - 10 ns allowable bit cell center and boundary jitter in data t arx2 --18ns carrier sense assertion delay t arx3 -240-ns invalid preamble bits after carrier sense asserts t arx4 1-2bits carrier sense deassertion delay t arx5 150 - 250 ns aui collision ci pair cycle time t acl1 85 100 115 ns ci pair rise and fall times t acl2 - - 10 ns ci pair return to zero from last positive transition t acl3 160 - - ns collision assertion delay t acl4 50 - 200 ns collision deassertion delay t acl5 150 - 300 ns do t atx1 t atx1 t atx2 t atx4 t atx3 1 0 0 0 figure 44. aui transmit di t arx1 t arx2 1 0 1 0 t arx3 t arx4 t arx5 t arx1 carrier sense (internal) figure 45. aui receive t acl1 ci t acl4 t acl5 collision (internal) t acl2 t acl2 t acl3 figure 46. aui collision
118 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet switching characteristics (continued) parameter symbol min typ max unit external boot prom access address active to memr t bprom1 20 - - ns memr active to csout low t bprom2 - - 35 ns memr inactive to csout high t bprom3 - - 40 ns eeprom eesk setup time relative to eecs t sks 100 - - ns eecs/elcs _b setup time wrt eesk t ccs 250 - - ns eedataout setup time wrt eesk t dis 250 - - ns eedataout hold time wrt eesk t dih 500 - - ns eedatain hold time wrt eesk t dh 10 - - ns eecs hold time wrt eesk t csh 100 - - ns min eecs low time during programming t cs 1000 - - ns sa [19:0] memr t bprom1 csout cs t bprom3 t bprom2 figure 47. external boot prom access t csh t cs t sks t css t dis t dih t dh eesk eecs eedata out eedata in (read) figure 48. eeprom
ds271pp4 119 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 7.5 10base-t wiring if a center tap transformer is used on the rxd+ and rxd- inputs, replace the pair of rr resistors with a single 2xrr resistor. the rt and rr resistors are 1% tolerance. the CS8900A supports 100, 120, and 150 ? unshielded twisted pair cables. the proper values of rt and rr, for a given cable impedance, are shown below: note: for 3.3v operation the turns ratio on txd+ and txd- is 1:2.5, rt is 8 ? for 100 ? cable and the 68pf cap changes to 560pf. cable impedance ( ? )rt ( ? ) rr ( ? ) 100 24.3 49.9 120 30.1 60.4 150 37.4 75 rt rt CS8900A td + td - txd + txd - 1 : 2 rj45 1 2 1 : 1 rd + rd - 3 6 0.01 f + rxd+ rxd- rr rr 0.01 f - 68 pf
120 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 7.6 aui wiring 7.7 quartz crystal requirements (if a 20 mhz quartz crystal is used, it must meet the following specifications) parameter min typ max unit parallel resonant frequency - 20 - mhz resonant frequency error (c l = 18 pf) -50 - +50 ppm resonant frequency change over operating temperature -40 - +40 ppm crystal capacitance - - 18 pf motional crystal capacitance - 0.022 - pf series resistance - - 50 ohm shunt capacitance - - 7 pf CS8900A do + do - 1 : 1 db15 3 10 tx 4 1 : 1 5 12 13 6 +12 v + ci + ci - 1 : 1 2 9 39.2 ? 39.2 ? col 0.01 uf - + di + di - 39.2 ? 39.2 ? rx 0.01 uf -
ds271pp4 121 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 8.0 characteristics/specifications - industrial 8.1 absolute maximum ratings (avss, dvss = 0 v, all voltages with respect to 0 v.) warning: normal operation is not guaranteed at these extremes. 8.2 recommended operating conditions (avss, dvss = 0 v, all voltages with respect to 0 v.) 8.3 dc characteristics (t a = 25 c; vdd = 5.0 v or vdd = 3.3v) notes: 1. with digital outputs connected to cmos loads. parameter symbol min max unit power supply digital analog d v dd a v dd -0.3 -0.3 6.0 6.0 v v input current (except supply pins) - 10.0 ma analog input voltage -0.3 ( a v dd +) + 0.3 v digital input voltage -0.3 ( d v dd ) + 0.3 v ambient temperature (power applied) -55 +125 c storage temperature -65 +150 c parameter symbol min max unit 5.0v power supply CS8900A-cq & -iq digital analog d v dd a v dd 4.75 4.75 5.25 5.25 v v 3.3v power supply CS8900A-cq3 & -iq3 digital analog d v dd a v dd 3.135 3.135 3.465 3.465 v v operating ambient temperature CS8900A-cq & -cq3 t a 0+70 c operating ambient temperature CS8900A-iq & -iq3 t a -40 +85 c parameter symbol min max unit crystal (when using external clock - square wave) xtal1 input low voltage v ixh -0.5 0.4 v xtal1 input high voltage v ixh 3.5 d v dd + 0.5 v xtal1 input low current i ixl -40 - a xtal1 input high current i ixh -40a power supply power supply current while active 5.0v i dd -55ma power supply current while active 3.3v i dd -45ma hardware standby mode current (note 1) i ddstndby -1.0ma hardware suspend mode current (note 1) i ddhwsus -100a software suspend mode current (note 1) i ddswsus -1.0ma
122 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet dc characteristics (continued) notes: 2. od24: open drain output with 24 ma drive od10: open drain output with 10 ma drive b24: bi-directional with 3-state output and 24 ma drive b4w: bi-directional with 3-state output, internal weak pullup, and 4 ma drive o24ts: 3-state output with 24 ma drive o4: output with 4 ma drive i: input iw: input with internal weak pullup parameter symbol min typ max unit digital inputs and outputs (note 2) output low voltage i ol = 24 ma od24, b24, o24ts i ol = 10 ma od10 i ol = 4 ma b4w, o4 v ol - - - - - - 0.4 0.4 0.4 v v v output low voltage (all outputs) v dd = 3.3v and t a = >70 cv ol 0.425 v output high voltage i oh = -12 ma b24 i oh = -2 ma b4w, o24ts, o4 v oh 2.4 2.4 - - - - v v output leakage current 0 v out v cc od24, od10, b24, o24ts b4w i ll -10 -20 - - 10 10 a input low voltage i, iw v il --0.8v input high voltage i, iw v ih 2.4 - - v input leakage current 0 v in v cc i iw i l -10 -20 - - 10 10 a 10base-t interface transmitter differential output voltage (peak) v od 2.2 - 2.8 v receiver normal squelch level (peak) v isq 300 - 525 mv receiver low squelch level (lorxsquelch bit set) v sql 125 - 290 mv aui interface transmitter differential output voltage (do+/do- peak) v aod 0.45 - 1.2 v transmitter undershoot voltage v aodu --100mv transmitter differential idle voltage (do+/do- peak) v idle --40mv receiver squelch level (di+/di- peak) v aisq 180 - 300 mv
ds271pp4 123 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 8.4 switching characteristics (t a = 25 c; v dd = 5.0 v or vdd = 3.3v) parameter symbol min typ max unit 16-bit i/o read, iochrdy not used address, aen, sbhe active to iocs16 low t ior1 - - 35 ns address, aen, sbhe active to ior active t ior2 10 - - ns ior low to sd valid t ior3 --135ns address, aen, sbhe hold after ior inactive t ior4 0- -ns ior inactive to active t ior5 35 - - ns ior inactive to sd 3-state t ior6 -30-ns 16-bit i/o read, with iochrdy ior active to iorchrdy inactive t ior7 -30-ns iochrdy low pulse width t ior8 125 - 175 ns iochrdy active to sd valid t ior9 --0ns sa [15:0], aen, sbhe valid address iocs16 in direction: in or out of chip ior sd [15:0] valid data out in out t ior1 t ior2 t ior3 t ior4 t ior5 t ior6 figure 49. 16-bit i/o read, iochrdy not used sa [15:0], aen, sbhe valid address iocs16 in direction: in or out of chip ior sd [15:0] valid data out in out iochrdy out t ior7 t ior8 t ior9 figure 50. 16-bit i/o read, with iochrdy
124 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet switching characteristics (continued) parameter symbol min typ max unit 16-bit memory read, iochrdy not used sa [19:0], sbhe , chipsel , active to memcs16 low t memr1 - - 30 ns address, sbhe , chipsel active to memr active t memr2 10 - - ns memr low to sd valid t memr3 --135ns address, sbhe , chipsel hold after memr inactive t memr4 0- -ns memr inactive to sd 3-state t memr5 -30-ns memr inactive to active t memr6 35 - - ns 16-bit memory read, with iochrdy memr low to iochrdy inactive t memr7 -35-ns iochrdy low pulse width t memr8 125 - 175 ns iochrdy active to sd valid t memr9 --0ns sa [19:0], sbhe, chipsel valid address memcs16 in direction: in or out of chip memr sd [15:0] valid data out in out t memr1 t memr2 t memr3 t memr4 t memr5 t memr6 figure 51. 16-bit memory read, iochrdy not used sa [19:0], sbhe, chipsel valid address memcs16 in direction: in or out of chip memr sd [15:0] valid data out in out iochrdy out t memr7 t memr8 t memr9 figure 52. 16-bit memory read, with iochrdy
ds271pp4 125 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet switching characteristics (continued) parameter symbol min typ max unit dma read dmackx active to ior active t dmar1 60 - - ns aen active to ior active t dmar2 10 - - ns ior active to data valid t dmar3 --135ns ior inactive to sd 3-state t dmar4 -30-ns ior n-1 high to dmarqx inactive t dmar5 - - 20 ns dmackx , aen hold after ior high t dmar6 20 ns 16-bit i/o write address, aen, sbhe valid to iocs16 low t iow1 - - 35 ns address, aen, sbhe valid to iow low t iow2 20 - - ns iow pulse width t iow3 110 - - ns sd hold after iow high t iow4 0- -ns iow low to sd valid t iow5 - - 10 ns iow inactive to active t iow6 35 - - ns address hold after iow high t iow7 0- -ns direction: in or out of chip sd[15:0] out ior dmarqx out in dmackx in aen in t dma1 ior n ior n-1 t dma2 valid data valid data valid data t dma3 t dma5 t dma4 t dma6 figure 53. 16-bit dma read figure 54. 16-bit i/o write sa [15:0], aen, sbhe valid address iocs16 in direction: in or out of chip iow sd [15:0] valid data in out in in t iow1 t iow2 t iow3 t iow4 t iow5 t iow6 t iow7
126 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet switching characteristics (continued) parameter symbol min typ max unit 16-bit memory write address, sbhe , chipsel valid to memcs16 low t memw1 - - 30 ns address, sbhe , chipsel valid to memw low t memw2 20 - - ns memw pulse width t memw3 110 - - ns memw low to sd valid t memw4 - - 40 ns sd hold after memw high t memw5 0- -ns address hold after memw inactive t memw6 0- -ns memw inactive to active t memw7 35 - - ns 10base-t transmit txd pair jitter into 100 ? load t ttx1 --8ns txd pair return to 50 mv after last positive transition t ttx2 --4.5s txd pair positive hold time at end of packet t ttx3 250 - - ns sa [19:0], sbhe, chipsel valid address memcs16 in direction: in or out of chip memw sd [15:0] valid data in out in in t memw3 t memw4 t memw5 t memw6 t memw7 t memw2 t memw1 figure 55. 16-bit memory write txd t ttx1 t ttx3 t ttx2 figure 56. 10base-t transmit
ds271pp4 127 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet switching characteristics (continued) parameter symbol min typ max unit 10base-t receive allowable received jitter at bit cell center t trx1 - - 13.5 ns allowable received jitter at bit cell boundary t trx2 - - 13.5 ns carrier sense assertion delay t trx3 -540-ns invalid preamble bits after assertion of carrier sense t trx4 1-2bits carrier sense deassertion delay t trx5 -270-ns 10base-t link integrity first transmitted link pulse after last transmitted packet t ln1 81624ms time between transmitted link pulses t ln2 81624ms width of transmitted link pulses t ln3 60 100 200 ns minimum received link pulse separation t ln4 2-7ms maximum received link pulse separation t ln5 25 - 150 ms last receive activity to link fail (link loss timer) t ln6 50 - 150 ms t trx3 rxd t trx5 t trx4 t trx1 t trx2 carrier sense (internal) figure 57. 10base-t receive rxd linkled txd t ln1 t ln2 t ln3 t ln4 t ln5 t ln6 figure 58. 10base-t link integrity
128 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet switching characteristics (continued) parameter symbol min typ max unit aui transmit do pair rise and fall times t atx1 --5ns do pair jitter at bit cell center t atx2 --0.5ns do pair positive hold time at start of idle t atx3 200 - - ns do pair return to 40 mvp after last positive transition t atx4 --8.0s aui receive di pair rise and fall time t arx1 - - 10 ns allowable bit cell center and boundary jitter in data t arx2 --18ns carrier sense assertion delay t arx3 -240-ns invalid preamble bits after carrier sense asserts t arx4 1-2bits carrier sense deassertion delay t arx5 150 - 250 ns aui collision ci pair cycle time t acl1 85 100 115 ns ci pair rise and fall times t acl2 - - 10 ns ci pair return to zero from last positive transition t acl3 160 - - ns collision assertion delay t acl4 50 - 200 ns collision deassertion delay t acl5 150 - 300 ns do t atx1 t atx1 t atx2 t atx4 t atx3 1 0 0 0 figure 59. aui transmit di t arx1 t arx2 1 0 1 0 t arx3 t arx4 t arx5 t arx1 carrier sense (internal) figure 60. aui receive t acl1 ci t acl4 t acl5 collision (internal) t acl2 t acl2 t acl3 figure 61. aui collision
ds271pp4 129 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet switching characteristics (continued) parameter symbol min typ max unit external boot prom access address active to memr t bprom1 20 - - ns memr active to csout low t bprom2 - - 35 ns memr inactive to csout high t bprom3 - - 40 ns eeprom eesk setup time relative to eecs t sks 100 - - ns eecs/elcs _b setup time wrt eesk t ccs 250 - - ns eedataout setup time wrt eesk t dis 250 - - ns eedataout hold time wrt eesk t dih 500 - - ns eedatain hold time wrt eesk t dh 10 - - ns eecs hold time wrt eesk t csh 100 - - ns min eecs low time during programming t cs 1000 - - ns sa [19:0] memr t bprom1 csout cs t bprom3 t bprom2 figure 62. external boot prom access t csh t cs t sks t css t dis t dih t dh eesk eecs eedata out eedata in (read) figure 63. eeprom
130 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 8.5 10base-t wiring if a center tap transformer is used on the rxd+ and rxd- inputs, replace the pair of rr resistors with a single 2xrr resistor. the rt and rr resistors are 1% tolerance. the CS8900A supports 100, 120, and 150 ? unshielded twisted pair cables. the proper values of rt and rr, for a given cable impedance, are shown below: note: for 3.3v operation the turns ratio on txd+ and txd- is 1:2.5, rt is 8 ? for 100 ? cable and the 68pf cap changes to 560pf. cable impedance ( ? )rt ( ? ) rr ( ? ) 100 24.3 49.9 120 30.1 60.4 150 37.4 75 rt rt CS8900A td + td - txd + txd - 1 : 2 rj45 1 2 1 : 1 rd + rd - 3 6 0.01 f + rxd+ rxd- rr rr 0.01 f - 68 pf
ds271pp4 131 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 8.6 aui wiring 8.7 quartz crystal requirements (if a 20 mhz quartz crystal is used, it must meet the following specifications) parameter min typ max unit parallel resonant frequency - 20 - mhz resonant frequency error (c l = 18 pf) -50 - +50 ppm resonant frequency change over operating temperature -40 - +40 ppm crystal capacitance - - 18 pf motional crystal capacitance - 0.022 - pf series resistance - - 50 ohm shunt capacitance - - 7 pf CS8900A do + do - 1 : 1 db15 3 10 tx 4 1 : 1 5 12 13 6 +12 v + ci + ci - 1 : 1 2 9 39.2 ? 39.2 ? col 0.01 uf - + di + di - 39.2 ? 39.2 ? rx 0.01 uf -
132 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 9.0 physical dimensions inches millimeters dim min max min max a --- 0.063 --- 1.60 a1 0.002 0.006 0.05 0.15 b 0.007 0.011 0.17 0.27 d 0.618 0.642 15.70 16.30 d1 0.547 0.555 13.90 14.10 e 0.618 0.642 15.70 16.30 e1 0.547 0.555 13.90 14.10 e* 0.016 0.024 0.40 0.60 l 0.018 0.030 0.45 0.75 0.000 7.000 0.00 7.00 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms026 100l tqfp package drawing e1 e d1 d 1 e l b a1 a
ds271pp4 133 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 10.0 glossary of terms 10.1 acronyms aui attachment unit interface crc cyclic redundancy check cs carrier sense csma/cd carrier sense multiple access with collision detection da destination address eeprom electrically erasable programmable read only memory eof end-of-frame fcs frame check sequence fdx full duplex ia individual address ipg inter-packet gap isa industry standard architecture la isa latchable address bus (la17 - la23) llc logical link control mac media access control mau medium attachment unit mib management information base rx receive sa source address or isa system address bus (sa0 - sa19) sfd start-of-frame delimiter snmp simple network management protocol sof start-of-frame sqe signal quality error tdr time domain reflectometer tx transmit utp unshielded twisted pair
134 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 10.2 definitions cyclic redundancy check the method used to compute the 32-bit frame check sequence (fcs). frame check sequence the 32-bit field at the end of a frame that contains the result of the cyclic redundancy check (crc). frame an ethernet string of data bits that includes the destination address (da), source address (sa), optional length field, logical link control data (llc data), pad bits (if needed) and frame check sequence (fcs). individual address the specific ethernet address assigned to a device attached to the ethernet media. inter-packet gap time interval between packets on the ethernet. minimum interval is 9.6 s. jabber a condition that results when a ethernet node transmits longer than between 20 ms and 150 ms. packet an ethernet string of data bits that includes the preamble, start-of-frame delimiter (sfd), destination address (da), source address (sa), optional length field, logical link control data (llc data), pad bits (if needed) and frame check sequence (fcs). a packet is a frame plus the preamble and sfd. receive collision a receive collision occurs when the ci+/ci- inputs are active while a packet is being received. applies only to the aui. signal quality error when transmitting on the aui, the mac expects to see a collision signal on the ci+/ci- pair within 64 bit times after the end of a transmission. if no collision occurs, there is said to be an "sqe error". applies only to the aui. slot time time required for an ethernet frame to cross a maximum length ethernet network. one slot time equals 512 bit times. transmit collision a transmit collision occurs when the receive inputs, rxd+/rxd- (10base-t) or ci+/ci- (aui) are active while a packet is being transmitted.
ds271pp4 135 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 10.3 acronyms specific to the CS8900A bufcfg buffer configuration - register b bufevent buffer event - register c busctl bus control - register 17 busst bus state - register 18 endec manchester encoder/decoder isq interrupt status queue - register 0 linectl ethernet line control - register 13 linest ethernet line status - register 14 rxcfg receive configuration - register 3 rxctl receive control - register 5 rxevent receive event - register 4 selfctl self control - register 15 selfst self status - register 16 testctl test control - register 19 txcfg transmit configuration - register 7 txcmd transmit command - register 9 txevent transmit event - register 8 10.4 terms specific to the CS8900A act-once bit a control bit that causes the CS8900A to take a certain action once when a logic "1" is written to that bit. to cause the action again, the host must rewrite a "1". committed receive frame a receive frame is said to be "committed" after the frame has been buffered by the CS8900A, and the host has been notified, but the frame has not yet been transferred by the host. committed transmit frame a transmit frame is said to be "committed" after the host has issued a transmit command, and the CS8900A has reserved buffer space and notified the host that it is ready for transmit. event or interrupt event the term "event" is used in this document to refer to something that can trigger an interrupt. items that are considered "events" are reported in the three event registers (rxevent, txevent, or bufevent) and in two counter-overflow bits (rxmiss and txcol). streamtransfer a method used to significantly reduce the number of interrupts to the host processor during block data transfers (patent pending). packetpage a unified, highly-efficient method of controlling and getting status of a peripheral controller in i/o or memory space.
136 ds271pp4 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet standby a feature of the CS8900A used to conserve power. when in standby mode, the CS8900A can be awakened either by 10base-t activity or host command. suspend a feature of the CS8900A used to conserve power. when in suspend mode, the CS8900A can be awakened only by host command. transfer the term "transfer" refers to moving frame data across the isa bus to or from the CS8900A. transmit request a transmit request is issued by the host to initiate the start of a new packet transmission. a transmit request consists of the following three steps in exactly the order shown: 1) the host writes a transmit command to the txcmd register (packetpage base + 0144h). 2) the host writes the transmit frame ? s length to the txlength register (packetpage base + 0146h). 3) the host reads busst (register 18) to see in the rdy4txnow bit (bit 8) is set. 10.5 suffixes specific to the CS8900A. these terms have meaning only at the end of a term: a accept cmd command cfg configure ctl control dis disable e enable h indicates the number is hexadecimal ie interrupt enable st status
ds271pp4 137 CS8900A crystal lan ? isa ethernet controller cirrus logic product datasheet 11.0 revision history 12 apr 2001 page 13
changed to
page 41 added bit definitions for revisions c and d page 56 changed to page 81 table 19: ! changed to ! page 86 table 23: "# changed to "#"

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